A New Approach for the Verification of Cache Coherence Protocols

We introduce a cache protocol verification technique based on a symbolic state expansion procedure. A global Finite State Machine (FSM) model characterizing the protocol behavior is built and protocol verification becomes equivalent to finding whether or not the global FSM may enter erroneous states. In order to reduce the complexity of the state expansion process, all the caches in the same state are grouped into an equivalence class and the number of caches in the class is symbolically represented by a repetition constructor. This symbolic representation is partly justified by the symmetry and homogeneity of cache-based systems. However, the key idea behind the representation is to exploit a unique property of cache coherence protocols: the fact that protocol correctness is not dependent on the exact number of cached copies. Rather, symbolic states only need to keep track of whether the caches have 0, 1, or multiple copies. The resulting symbolic state expansion process only takes a few steps and verifies the protocol for any system size. Therefore, it is more efficient and reliable than current approaches. The verification procedure is first applied to the verification of five existing protocols under the assumption of atomic protocol transitions. A simple snooping protocol on a split-transaction shared bus is also verified to illustrate the extension of our approach to protocols with nonatomic transitions. >

[1]  Olivier Coudert,et al.  Verification of Synchronous Sequential Machines Based on Symbolic Execution , 1989, Automatic Verification Methods for Finite State Systems.

[2]  Larry Rudolph,et al.  Dynamic decentralized cache schemes for mimd parallel processors , 1984, ISCA '84.

[3]  David L. Dill,et al.  Efficient verification of symmetric concurrent systems , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[4]  Michel Dubois,et al.  The verification of cache coherence protocols , 1993, SPAA '93.

[5]  Gregor von Bochmann,et al.  A Unified Method for the Specification and Verification of Protocols , 1977, IFIP Congress.

[6]  Jean Christophe Madre,et al.  Proving circuit correctness using formal comparison between expected and extracted behaviour , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[7]  W.M. vanCleemput,et al.  Computer hardware description languages and their applications , 1979, 16th Design Automation Conference.

[8]  James K. Archibald,et al.  Cache coherence protocols: evaluation using a multiprocessor simulation model , 1986, TOCS.

[9]  Daniel Brand,et al.  Towards Analyzing and Synthesizing Protocols , 1980, IEEE Trans. Commun..

[10]  David L. Dill,et al.  Better verification through symmetry , 1996, Formal Methods Syst. Des..

[11]  David L. Dill,et al.  Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic , 1990, CAV.

[12]  Laxmi N. Bhuyan,et al.  A Formal Specification and Verification Technique for Cache Coherence Protocols , 1992, ICPP.

[13]  Paul Feautrier,et al.  A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.

[14]  Michel Dubois,et al.  An Integrated Methodology for the Verification of Directory-Based Cache Protocols , 1994, 1994 International Conference on Parallel Processing Vol. 1.

[15]  A. Danthine,et al.  Protocol Representation with Finite-State Models , 1980, IEEE Trans. Commun..

[16]  Pong Fong Symbolic state model: a new approach for the verification of cache coherence protocols , 1996 .

[17]  Somesh Jha,et al.  Exploiting symmetry in temporal logic model checking , 1993, Formal Methods Syst. Des..

[18]  Alan J. Hu,et al.  Protocol verification as a hardware design aid , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[19]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[20]  Gerard J. Holzmann Algorithms for automated protocol verification , 1990, AT&T Technical Journal.

[21]  A. Prasad Sistla,et al.  Symmetry and model checking , 1993, Formal Methods Syst. Des..

[22]  Brent Hailpern Verifying Concurrent Processes Using Temporal Logic , 1982, Lecture Notes in Computer Science.

[23]  Yasushi Wakahara,et al.  An Acyclic Expansion Algorithm for Fast Protocol Validation , 1988, IEEE Trans. Software Eng..

[24]  Larry Rudolph,et al.  Dynamic decentralized cache schemes for mimd parallel processors , 1984, ISCA 1984.

[25]  Somesh Jha,et al.  Verification of the Futurebus+ cache coherence protocol , 1993, Formal Methods Syst. Des..

[26]  Gregor von Bochmann,et al.  Formal Methods in Communication Protocol Design , 1980, IEEE Trans. Commun..