论文信息 - Radio receiver front-end using time-based all-digital ADC (TAD)

Radio receiver front-end using time-based all-digital ADC (TAD)

A direct-conversion RF-receiver IC implemented in 65nm CMOS, which has an RF front-end and all-digital differential time-based analog-to-digital converter (TAD) with 4-time-interleave technique for high resolution, is presented. The RF front-end contains passive mixers using wideband gm-cells and switches. When OFDM 16QAM RF signal (input power: -45.4dBm, BW: 20MHz) of 500M, 1.5G, and 2.5GHz is demodulated, EVM is -27.8, -27.4, and -17.3dB, respectively.

[1] Frank Opteynde. A maximally-digital radio receiver front-end , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2] Tomohito Terasawa,et al. An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-μm CMOS , 2010, 2010 Proceedings of ESSCIRC.

[3] O. Moreira-Tamayo,et al. All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[4] Y. Makino,et al. An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering , 2003, IEEE J. Solid State Circuits.

[5] Michiel Steyaert,et al. A 0.02mm2 65nm CMOS 30MHz BW all-digital differential VCO-based ADC with 64dB SNDR , 2010, 2010 Symposium on VLSI Circuits.