VLSI Implementation of ESF and QTL Lightweight Ciphers

In order to provide security in resource scare environment, various lightweight ciphers are proposed. Many optimized architectural designs for these ciphers are presented by several authors to enhance the compatibility with lightweight domain. In this work, in order to provide security in lightweight environment, three optimized hardware architectures of eight-sided fortress (ESF) and QTL ciphers are proposed. Two architectures for ESF cipher are presented based on different S-box generation techniques. RAM-based hardware design of QTL cipher is also presented. Designs are evaluated and compared in various FPGA platforms, on the basis of resource consumption, performance and power requirement for their implementation. ESF architecture with RAM-based S-box requires least resource consumption for its implementation.