Implementation of a cycle by cycle variable speed processor
暂无分享,去创建一个
[1] Yvon Savaria,et al. Optimal design of synchronous circuits using software pipelining techniques , 2001, TODE.
[2] Saraju P. Mohanty,et al. Datapath scheduling using dynamic frequency clocking , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.
[3] Ran Ginosar,et al. Adaptive synchronization , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).
[4] Augustus K. Uht,et al. Uniprocessor performance enhancement through adaptive clock frequency control , 2005, IEEE Transactions on Computers.
[5] Charles E. Leiserson,et al. Retiming synchronous circuitry , 1988, Algorithmica.
[6] Y. Savaria,et al. A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications , 2004, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..
[7] Alessandro Trifiletti,et al. A low-power microcontroller with on-chip self-tuning digital clock-generator for variable-load applications , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).