The relevance of deeply-scaled FET threshold voltage shifts for operation lifetimes

In nm-sized FET devices with just a few gate oxide defects, the typically measured threshold voltage shifts are not obviously correlated with the device behavior at high gate bias. The largest shifts observed at the threshold voltage after the capture of a single carrier are reduced at higher gate biases. This degradation-mitigating effect is further shown to be amplified at lower channel doping. The understanding gained from 3D numerical simulations is captured in a simple analytic description of a single trapped-charge impact on the FET characteristics in the entire gate bias range. Potential use is illustrated in an improved lifetime projection and in circuit simulations of time-dependent variability.

[1]  K. Takeuchi,et al.  Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude , 2006, 2009 Symposium on VLSI Technology.

[2]  R. Degraeve,et al.  Correlation of single trapping and detrapping effects in drain and gate currents of nanoscaled nFETs and pFETs , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[3]  G. Groeseneken,et al.  From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[4]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[5]  A. Kumar,et al.  Suppression of VT variability degradation induced by NBTI with RDF control , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[6]  B. Kaczer,et al.  Recent advances in understanding the bias temperature instability , 2010, 2010 International Electron Devices Meeting.

[7]  G. Groeseneken,et al.  Atomistic approach to variability of bias-temperature instability in circuit simulations , 2011, 2011 International Reliability Physics Symposium.

[8]  Modeling statistical distribution of random telegraph noise magnitude , 2011, 2011 International Conference on Simulation of Semiconductor Processes and Devices.

[9]  N. Horiguchi,et al.  Response of a single trap to AC negative Bias Temperature stress , 2011, 2011 International Reliability Physics Symposium.

[10]  N. Horiguchi,et al.  Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[11]  M. Alam,et al.  Analyzing the distribution of threshold voltage degradation in nanoscale transistors by using reaction-diffusion and percolation theory , 2011 .

[12]  Tibor Grasser,et al.  Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Vincent Huard,et al.  A bottom-up approach for System-On-Chip reliability , 2011, Microelectron. Reliab..

[14]  J. Martin-Martinez,et al.  Time-dependent variability of high-k based MOS devices: Nanoscale characterization and inclusion in circuit simulators , 2011, 2011 International Electron Devices Meeting.

[15]  李幼升,et al.  Ph , 1989 .

[16]  G. Groeseneken,et al.  Time and workload dependent device variability in circuit simulations , 2011, 2011 IEEE International Conference on IC Design & Technology.

[17]  R. Wong,et al.  Impact of NBTI Induced Statistical Variation to SRAM Cell Stability , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[18]  Miss A.O. Penney.  (b) , 1974, The New Yale Book of Quotations.

[19]  T. Grasser,et al.  ‘Atomistic’ simulation of RTS amplitudes due to single and multiple charged defect states and their interactions , 2010, IEEE International Integrated Reliability Workshop Final Report.

[20]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[21]  S. Natarajan,et al.  Impact of negative bias temperature instability on digital circuit reliability , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[22]  B. Kaczer,et al.  Analytic modeling of the bias temperature instability using capture/emission time maps , 2011, 2011 International Electron Devices Meeting.