SSTL IO Standard Based Energy Efficient Digital Clock Design on 28nm FPGA

In this paper we have aimed to have an energy efficient digital clock design. Digital clock is a type of clock that displays time digitally. The code has been implemented in Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform using Kintex-7 FPGA family using different SSTL IOStandards. Comparison between different SSTL IOStandard has been done to achieve minimum IO power. Via SSTL technology, we achieve green computing with respect to low voltage impedance. In this work we are testing our digital clock design with different SSTL IOStandards such as SSTL15, SSTL18_II, SSTL135, SSTL12, SSTL18_I. In this work we have taken constant value of air flow and heat sink. Airflow has been kept 250 LFM and medium Heat sink. The design consists of five inputs and six outputs. At th end we concluded that there is 24-35% saving in total power dissipation with 1.2 GHz when compared with 2.2 GHz.