Automatic hardware language transformation system

The invention discloses an automatic hardware language transformation system comprising a lexical analysis module, a syntactic analysis and semantic check module, an intermediate representation storage unit and a transformation module. The lexical analysis module is used for transforming a character sequence including keywords, identifiers, constants, character strings, operators and annotations in the Verilog language into tokens. The syntactic analysis and semantic check module is used for realizing syntactic analysis by recognizing structures of expressions, statements, process blocks, modules and the like in a Verilog program according to syntax rules of the Verilog language specified in Bison while performing the semantic check. The intermediate representation storage unit is used for realizing intermediate representation of the different structural bodies of a Verilog source file by the unit of modules. The transformation module is used for transforming the Verilog language into the MSVL (modeling, simulation and verification language) according language transformation rules between the Verilog language and the MSVL.