Van der Waals negative capacitance transistors
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Lu You | Peng Yu | Fucai Liu | Xun Cao | Qingsheng Zeng | Zheng Liu | L. You | Junling Wang | Qingsheng Zeng | Yizhong Huang | Chao Zhu | Jiadong Zhou | Zheng Liu | Fucai Liu | Xun Cao | Peng Yu | Junling Wang | Yizhong Huang | Qundong Fu | Xiaowei Wang | Jiadong Zhou | Qundong Fu | Chao Zhu | Ya Deng | Xiaowei Wang | Zhendong Lei | Ya Deng | Zhendong Lei
[1] H. Peng,et al. Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches , 2018, Science.
[2] P. Ye,et al. Ferroelectric Field-Effect Transistors Based on MoS2 and CuInP2S6 Two-Dimensional van der Waals Heterostructure. , 2018, ACS nano.
[3] Mengwei Si,et al. Steep-Slope WSe2 Negative Capacitance Field-Effect Transistor. , 2018, Nano letters.
[4] Yogesh Singh Chauhan,et al. Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures , 2018, IEEE Transactions on Electron Devices.
[5] Peng Zhou,et al. Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating , 2017, npj 2D Materials and Applications.
[6] H. Peng,et al. Out-of-Plane Piezoelectricity and Ferroelectricity in Layered α-In2Se3 Nanoflakes. , 2017, Nano letters.
[7] S. Haigh,et al. Observing Imperfection in Atomic Interfaces for van der Waals Heterostructures. , 2017, Nano letters.
[8] S. Salahuddin,et al. Sustained Sub-60 mV/decade Switching via the Negative Capacitance Effect in MoS2 Transistors. , 2017, Nano letters.
[9] Meng-Fan Chang,et al. Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET , 2017, IEEE Transactions on Electron Devices.
[10] Kaushik Roy,et al. Design Space Exploration of Hysteresis-Free HfZrOx-Based Negative Capacitance FETs , 2017, IEEE Electron Device Letters.
[11] Saurabh Sinha,et al. Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM , 2017, IEEE Electron Device Letters.
[12] Joshua H. Carpenter,et al. Flexible Inorganic Ferroelectric Thin Films for Nonvolatile Memory Devices , 2017 .
[13] Hong Zhou,et al. Steep-slope hysteresis-free negative capacitance MoS2 transistors , 2017, Nature Nanotechnology.
[14] Zhenyu Zhang,et al. Prediction of intrinsic two-dimensional ferroelectrics in In2Se3 and other III2-VI3 van der Waals materials , 2017, Nature Communications.
[15] Jaehyun Lee,et al. Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications , 2017, IEEE Transactions on Electron Devices.
[16] Ole Bethge,et al. A microprocessor based on a two-dimensional semiconductor , 2016, Nature Communications.
[17] Sergei V. Kalinin,et al. Size-effect in layered ferrielectric CuInP2S6 , 2016 .
[18] Moon J. Kim,et al. MoS2 transistors with 1-nanometer gate lengths , 2016, Science.
[19] G. Pahwa,et al. Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.
[20] Zhihui Cheng,et al. Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer , 2016 .
[21] Hua Zhang,et al. Two-dimensional semiconductors for transistors , 2016 .
[22] P. Ajayan,et al. Room-temperature ferroelectricity in CuInP2S6 ultrathin flakes , 2016, Nature Communications.
[23] Akira Toriumi,et al. Structural advantages of silicon-on-insulator FETs over FinFETs in steep subthreshold-swing operation in ferroelectric-gate FETs , 2016 .
[24] Sergei V. Kalinin,et al. Quantitative Analysis of the Local Phase Transitions Induced by Laser Heating. , 2015, ACS nano.
[25] Masaharu Kobayashi,et al. Device design guideline for steep slope ferroelectric FET using negative capacitance in sub-0.2V operation: Operation speed, material requirement and energy efficiency , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).
[26] Sergei V. Kalinin,et al. CuInP₂S₆ Room Temperature Layered Ferroelectric. , 2015, Nano letters.
[27] Bo Liu,et al. Charge trapping at the MoS2-SiO2 interface and its effects on the characteristics of MoS2 metal-oxide-semiconductor field effect transistors , 2015 .
[28] Kaustav Banerjee,et al. A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect , 2014, IEEE Transactions on Electron Devices.
[29] Hao Wu,et al. Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics , 2014, Nature Communications.
[30] Xu Du,et al. Extrinsic and intrinsic charge trapping at the graphene/ferroelectric interface. , 2014, Nano letters.
[31] Lijun Wu,et al. Interface-induced nonswitchable domains in ferroelectric thin films , 2014, Nature Communications.
[32] Vibhor Singh,et al. Deterministic transfer of two-dimensional materials by all-dry viscoelastic stamping , 2013, 1311.4829.
[33] Jing Guo,et al. On Monolayer ${\rm MoS}_{2}$ Field-Effect Transistors at the Scaling Limit , 2013, IEEE Transactions on Electron Devices.
[34] Saul Rodriguez,et al. A Comprehensive Graphene FET Model for Circuit Design , 2013, IEEE Transactions on Electron Devices.
[35] Chenming Hu,et al. Device design considerations for ultra-thin body non-hysteretic negative capacitance FETs , 2013, 2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S).
[36] Joerg Appenzeller,et al. WSe2 field effect transistors with enhanced ambipolar characteristics , 2013 .
[37] Cheolmin Park,et al. Flexible Non‐Volatile Ferroelectric Polymer Memory with Gate‐Controlled Multilevel Operation , 2012, Advanced materials.
[38] J. Kong,et al. Integrated circuits based on bilayer MoS₂ transistors. , 2012, Nano letters.
[39] Sergei V. Kalinin,et al. Switchable induced polarization in LaAlO3/SrTiO3 heterostructures. , 2012, Nano letters.
[40] S. Shi,et al. Effect of strain and deadlayer on the polarization switching of ferroelectric thin film , 2011 .
[41] Stephen Jesse,et al. The role of electrochemical phenomena in scanning probe microscopy of ferroelectric thin films. , 2011, ACS nano.
[42] A. Radenović,et al. Single-layer MoS2 transistors. , 2011, Nature nanotechnology.
[43] Changgu Lee,et al. Anomalous lattice vibrations of single- and few-layer MoS2. , 2010, ACS nano.
[44] S. Datta,et al. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. , 2008, Nano letters.
[45] R. Cavin,et al. Nanoelectronics: negative capacitance to the rescue? , 2008, Nature nanotechnology.
[46] Yuan Taur,et al. Fundamentals of Modern VLSI Devices , 1998 .
[47] P. McMillan,et al. Pressure-induced phase transition in ferrielectric CuInP2S6 , 1998 .
[48] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[49] P. Ye,et al. A Closed Form Analytical Model of Back-Gated 2-D Semiconductor Negative Capacitance Field Effect Transistors , 2018, IEEE Journal of the Electron Devices Society.
[50] P. Su,et al. Interface discrete trap induced variability for negative capacitance FinFETs , 2018, 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).