Semiconductor memory device and method of arranging signal lines of the same
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The present invention discloses a signal line arrangement method of a semiconductor memory device and the device. The device data of the sub-memory cell array, the bit line pair including the memory cells selected by connection between the pair of bit lines and the sub-word line in response to a signal transmitted to the sub-word lines and column select signal line provided, and the bit line pairs to a sub-word line driver, for sensing a selection of a sub word line by combining the signals transmitted from the signal of the main word line is transmitted from the bit line sense amplifier, and a word select signal line to amplify and transmitting data between the local data line pair, and covering the memory cell array, and a memory cell array for transmitting data between the local data line pairs and the global data line pair as a whole for applying a voltage required for the memory cells, provided with electrodes, a local data line pairs of sub-electrode on the first floor of the top word Line and arranged in the same direction, the column selection signal lines and the global data line pairs are arranged in the same direction as the bit line on the second floor of the upper portion of the electrode, the word selection signal lines and main word lines of the electrode top 3 characterized in that disposed in the same direction as the sub-word line to the floor. Therefore, the leak current flowing from the electrodes to the word lines is prevented the drop of the level of the electrode voltage.