Latch-up test measurement for long duration space missions

Long duration space missions require extremely high reliable components that must guarantee components functionality without incurring in damaging effects. When Integrated Circuits (ICs) are considered, radiation hardened technology should be mandatorily adopted, since it allows to adequately protect against Single Event Latchup (SEL). In this paper we present a complete test measurement experimental setup in order to measure the SEL occurrences at high temperature conditions. The SEL test setup and the executed experiments are described. The experimental environment has been used to test SEL effects in Gate Arrays MG2 Radiation Hardened technology with respect to strike of heavy ions. We performed a complete radiation test at GANIL radiation facility, executed at high temperature by monitoring current absorption and analyzing the functionality of the MSDRX ASIC core. Experimental results show that a drastic improvement of the device SEL sensitivity is observed for high power supply voltages.

[1]  G. Bruguier,et al.  Single particle-induced latchup , 1996 .

[2]  M. Shoga,et al.  Radiation hardness evaluation of a class V 32-bit floating-point digital signal processor , 2005, IEEE Radiation Effects Data Workshop, 2005..

[3]  J.M. Hutson,et al.  The Effects of Angle of Incidence and Temperature on Latchup in 65 nm Technology , 2007, IEEE Transactions on Nuclear Science.

[4]  G. L. Hash,et al.  Effects of particle energy on proton-induced single-event latchup , 2005, IEEE Transactions on Nuclear Science.

[5]  H.P. Zappe,et al.  A transient analysis of latchup in bulk CMOS , 1983, IEEE Transactions on Electron Devices.

[6]  J. F. Leavy,et al.  Radiation-Induced Integrated Circuit Latchup , 1969 .

[7]  C. Hafer,et al.  Single event effects testing of a PLL and LVDS in a RadHard-by-design 0.25-micron ASIC , 2005, IEEE Radiation Effects Data Workshop, 2005..

[8]  G. L. Hash,et al.  Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits , 2007, IEEE Transactions on Nuclear Science.