A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter (ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital Converter (TDC) that is robust against process variation and suitable for embedding within a 3-bit ADC is discussed and its performance evaluated. Simulation shows that when the TDC is designed in a 90nm CMOS process it is capable of a DNL and INL less than ±0.040L5B and ±0.015LSB, respectively, for 9mW of power consumption at 5GS/s with a 6.25ps resolution.

[1]  Michael P. Flynn,et al.  A 9b 14µW 0.06mm2 PPM ADC in 90nm digital CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Kenneth A. Townsend,et al.  A 5GS/s voltage-to-time converter in 90nm CMOS , 2009, 2009 European Microwave Integrated Circuits Conference (EuMIC).

[3]  Jan Craninckx,et al.  A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS , 2009, IEEE Journal of Solid-State Circuits.

[4]  C.-I.H. Chen,et al.  A High Spurious-Free Dynamic Range 4-bit ADC with Nyquist Signal Bandwidth for Wideband Communications , 2007, 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007.

[5]  R. S. Parthasarathy,et al.  Double pass-transistor logic for high performance wave pipeline circuits , 1998, Proceedings Eleventh International Conference on VLSI Design.

[6]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.