The lithography technology for the 32 nm HP and beyond

When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. In this paper, we will explore the capability of using the double pattern technique (DPT) to extend the resolution capability of the water-based immersion lithography and examine the readiness of EUV to carry the lithography resolution capability beyond the 32 nm HP. The DPT, whether done in two litho and etch steps (LELE) or using the side wall spacer and sacrificial layer technique (SPT), will require significant improvement in CDU and overlay process control performance. We will report the experimental results in exploring the CDU and overlay performance of the LELE and the SPT options. We will also demonstrate the need to perform full field and full wafer process corrections to compensate for dual CDU populations and overlay entangled CDU variations. Furthermore, we will make an assessment of EUV readiness to further extend the lithography resolution capability beyond the 32 nm half-pitch.

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