Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.

[1]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[2]  Christos A. Papachristou,et al.  An ILP formulation to optimize test access mechanism in system-on-chip testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[3]  Zebo Peng,et al.  An integrated system-on-chip test framework , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[4]  Sujit Dey,et al.  A fast and low cost testing technique for core-based system-on-chip , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[5]  H. P. Williams,et al.  Model Building in Mathematical Programming , 1979 .

[6]  Srinivas Raman,et al.  Direct access test scheme-design of block and core cells for embedded ASICs , 1990, Proceedings. International Test Conference 1990.

[7]  Yervant Zorian,et al.  Wrapper design for embedded core test , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[8]  Yervant Zorian,et al.  Testing embedded-core based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Peter Harrod,et al.  Testing reusable IP-a case study , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[10]  Nur A. Touba,et al.  Using Partial Isolation Rings to Test Core-Based Designs , 1997, IEEE Des. Test Comput..

[11]  Erik Jan Marinissen,et al.  A structured and scalable mechanism for test access to embedded reusable cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[12]  Krishnendu Chakrabarty.  Design of system-on-a-chip test access architectures using integer linear programming , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[13]  Prab Varma,et al.  A structured test re-use methodology for core-based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  ChakrabartyKrishnendu.  Optimal test access architectures for system-on-a-chip , 2001 .

[15]  Yervant Zorian,et al.  On using IEEE P1500 SECT for test plug-n-play , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[16]  E.J. Marinissen,et al.  Scan chain design for test time reduction in core-based ICs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[17]  Yervant Zorian,et al.  On IEEE P1500's Standard for Embedded Core Test , 2002, J. Electron. Test..

[18]  Richard M. Wilson,et al.  A course in combinatorics , 1992 .

[19]  Krishnendu Chakrabarty.  Design of system-on-a-chip test access architectures under place-and-route and power constraints , 2000, Proceedings 37th Design Automation Conference.

[20]  John D. C. Little,et al.  On model building , 1993 .