Programmable logic array

The present invention relates to programmable logic arrays. Programmable logic array according to the present invention comprises the end plane and the OR plane. Said end plane, and is operated in synchronization with the clock signal, in response to the first input signal to generate a logical product signal. Wherein the OR plane, and the first input signals being input to the second input signal which is later input of all, in response to a first logic product signal that is not dependent on the second input signal generate a first logical signal, wherein second input signal to the second in response to a logical product signal, which depends on generating a second logical signal, and thus the logic state of the second input signal and the second logical sum signal to vary a first logical signal. According to the invention, by the late input signal and can increase the operating speed of the programmable logic arrays, it is possible to reduce the standby power.