An accurate RF CMOS gate resistance model compatible with HSPICE

Two important models, which are crucial to the RF CMOS, are the gate resistance and substrate resistance. Both are closely related to the development of accurate device and/or circuit models, such as noise. From the experimental observations, we found that the gate resistance depends largely on the bias and temperature. It will greatly impact the device performance at high frequency. For the first time, a simple and analytical physical-based gate resistance model is developed in this paper and has been implemented in Spice. The gate resistance is modeled by a parallel interconnection of the intrinsic gate resistance and a resistance coupled from the channel. The Spice simulation result of this model is more accurate than that of using a constant R/sub g/ model. A constant R/sub g/ model will overestimate the value of Y/sub 11/. While, in contrast, the proposed nonlinear gate resistance model with both bias and frequency dependent feature can achieve very good accuracy.

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