High-level macro-modeling and estimation techniques for switching activity and power consumption

We present efficient techniques for estimating switching activity and power consumption at the register-transfer level (RTL), using a combination of macro-modeling for datapath blocks, and control logic analysis techniques based on partial delay information. Previous work on estimating switching activity and power at the RTL has ignored the presence of glitches at various datapath and control signals. We demonstrate that glitches can form a significant component of the switching activity at signals in typical RTL circuits. In particular, for control-flow intensive designs, we show that the controller substantially affects the activity and power consumption in the datapath due to the presence of glitches at control signals. Since the final implementation of the controller is not available during high-level design iterations, we develop techniques that estimate glitching activity at control signals using control expressions and partial delay information. For datapath blocks that operate on word-level data, we construct piecewise linear models that capture the variation of output glitching activity and power consumption with various word-level parameters like mean, standard deviation, spatial and temporal correlations, and glitching activity at the block's inputs. For RTL blocks that operate on bit vectors that need not have an associated word-level value, we present accurate bit-level modeling techniques for glitching activity as well as power consumption. This allows us to perform accurate power estimation for control-flow intensive circuits, where most of the power consumed is dissipated in non-arithmetic components like multiplexers, registers, vector logic operators, etc. Experimental results on several RTL designs demonstrate the accuracy of the proposed estimation techniques. Our RTL power estimator produced estimates that were within 7% of those produced by an in-house power analysis tool on the final gate-level implementation, while being over 50/spl times/ faster than its gate-level counterpart.

[1]  Farid N. Najm,et al.  Towards a high-level power estimation capability , 1995, ISLPED '95.

[2]  Andreas Kuehlmann,et al.  Timing analysis in high-level synthesis , 1992, ICCAD.

[3]  Massoud Pedram,et al.  Register Allocation and Binding for Low Power , 1995, 32nd Design Automation Conference.

[4]  Niraj K. Jha,et al.  High-level synthesis of low-power control-flow intensive circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Jan M. Rabaey,et al.  Activity-sensitive architectural power analysis for the control path , 1995, ISLPED '95.

[6]  S. Gupta,et al.  Power Macromodeling For High Level Power Estimation , 1997, Proceedings of the 34th Design Automation Conference.

[7]  Sujit Dey,et al.  Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications , 1994, 31st Design Automation Conference.

[8]  Kaushik Roy,et al.  A power macromodeling technique based on power sensitivity , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[9]  Mary Jane Irwin,et al.  Energy characterization based on clustering , 1996, DAC '96.

[10]  Roger Sauter,et al.  Introduction to Probability and Statistics for Engineers and Scientists , 2005, Technometrics.

[11]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[12]  L. Benini,et al.  Lookup table power macro-models for behavioral library components , 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

[13]  Viraphol Chaiyakul,et al.  Accurate layout area and delay modeling for system level design , 1992, ICCAD.

[14]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[15]  Farid N. Najm,et al.  Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuitsy , 1995, 32nd Design Automation Conference.

[16]  E. Macii,et al.  High-level Power Modeling, Estimation, And Optimization , 1997, Proceedings of the 34th Design Automation Conference.

[17]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.

[18]  Niraj K. Jha,et al.  SCALP: an iterative-improvement-based low-power data path synthesis system , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Luca Benini,et al.  Regression Models for Behavioral Power Estimation , 1998, Integr. Comput. Aided Eng..

[20]  D. I. Cheng,et al.  A new hybrid methodology for power estimation , 1996, DAC '96.

[21]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[22]  Donald E. Knuth,et al.  The art of computer programming. Vol.2: Seminumerical algorithms , 1981 .

[23]  Sujit Dey,et al.  Clock Period Optimization During Resource Sharing and Assignment , 1994, 31st Design Automation Conference.

[24]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[25]  Jerry Frenkil.  Tools and methodologies for low power design , 1997, DAC.

[26]  Chi-Ying Tsui,et al.  Towards the capability of providing power-area-delay trade-off at the register transfer level , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[27]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[28]  Chi-Ying Tsui,et al.  Towards the capability of providing power-area-delay trade-off at the register transfer level , 1998, ISLPED '98.

[29]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[30]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[31]  Massoud Pedram,et al.  Statistical sampling and regression analysis for RT-Level power evaluation , 1996, Proceedings of International Conference on Computer Aided Design.

[32]  Nikil D. Dutt,et al.  Rapid estimation for parameterized components in high-level synthesis , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[33]  Farid N. Najm,et al.  High-level area and power estimation for VLSI circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[34]  Farid N. Najm,et al.  High-level power estimation and the area complexity of Boolean functions , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[35]  Klaus D. Müller-Glaser,et al.  Estimating essential design characteristics to support project planning for ASIC design management , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[36]  Kees G. W. Goossens,et al.  The Petrol approach to high-level power estimation , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[37]  Farid N. Najm,et al.  Transition density, a stochastic measure of activity in digital circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[38]  G. Casella,et al.  Statistical Inference , 2003, Encyclopedia of Social Network Analysis and Mining.

[39]  Sujit Dey,et al.  Provably correct high-level timing analysis without path sensitization , 1994, ICCAD.

[40]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[41]  Toshinori Sato,et al.  Evaluation of architecture-level power estimation for CMOS RISC processors , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[42]  Radu Marculescu,et al.  Information theoretic measures of energy consumption at register transfer level , 1995, ISLPED '95.

[43]  Srinivas Devadas,et al.  Computer-Aided Design Techniques for Low Power Sequential Logic Circuits , 1996 .

[44]  Niraj K. Jha,et al.  Register-transfer level estimation techniques for switching activity and power consumption , 1996, ICCAD 1996.

[45]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..