Realistic Yield Simulation for VLSIC Structural Failures

This paper presents a methodology for determining the probability of structural failures for VLSI circuits. An analytically based approach is used to perform simulations accurately and efficiently. This approach considers the specific IC layout and accounts for most of the fault mechanisms caused by global geometrical variations and local defects. A hierarchical model is proposed to describe the defect statistics including clustering. Strict analytical methods are used to find probabilities of failure for simple layout patterns. Then, the probability of failure for macrocells are calculated hierarchically. This methodology has been implemented in a CAD tool called RYE (Realistic Yield Evaluator). To demonstrate the effectiveness of this tool, the simulation results of several examples and the CPU time comparisons with Monte Carlo methods are also presented in this paper.

[1]  J. W. Lathrop,et al.  Defect analysis and yield degradation of integrated circuits , 1974 .

[2]  D. M. H. Walker,et al.  VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  S. R. Hofstein,et al.  The silicon insulated-gate field-effect transistor , 1963 .

[4]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[5]  Andrzej J. Strojwas,et al.  A Statistical Design Rule Developer , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  S. M. Hu,et al.  Some considerations in the formulation of IC yield statistics , 1979 .

[7]  Andrzej J. Strojwas,et al.  VLSI Yield Prediction and Estimation: A Unified Framework , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[9]  R. M. Warner.  Applying a composite model to the IC yield problem , 1974 .

[10]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .

[11]  C. H. Stapper.  Comments on “some considerations in the formulation of IC yield statistics” , 1981 .

[12]  Charles H. Stapper,et al.  Modeling of Integrated Circuit Defect Sensitivities , 1983, IBM J. Res. Dev..

[13]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.