Transistor Fault Coverage for Self-Testing CMOS Checkers

Several realistic transistor fault models were applied to circuit-level simulation models of code checkers in order to investigate the run-time fault testing capability. Various implementations of checkers designed for the detection of stuck-at faults were examined. A coverage varying from 99% to 100% was obtained for transistor terminal short faults and from 40% to 85% for open faults. A minimum set of four fault models for simulation-based evaluation of the self-testing property is proposed.

[1]  Edward J. McCluskey,et al.  Bridging, transition, and stuck-open faults in self-testing CMOS checkers , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

[2]  Edward J. McCluskey,et al.  "RESISTIVE SHORTS" WITHIN CMOS GATES , 1991, 1991, Proceedings. International Test Conference.

[3]  Yves Crouzet,et al.  Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.

[4]  R. E. Oakley,et al.  CASMOS-an accurate MOS model with geometry-dependent parameters: I , 1981 .

[5]  Niraj K. Jha,et al.  TOTALLY SELF-CHECKING MOS CIRCUITS UNDER REALISTIC PHYSICAL FAILURES. , 1984 .

[6]  Wojciech Maly,et al.  Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.

[7]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[8]  C. Timoc,et al.  Logical Models of Physical Failures , 1983, ITC.

[9]  J. M. Soden,et al.  Electrical properties and detection methods for CMOS IC defects , 1989, [1989] Proceedings of the 1st European Test Conference.

[10]  E. G. Chester,et al.  Design of a reliable and self-testing VLSI datapath using residue coding techniques , 1986 .

[11]  Daniel P. Siewiorek,et al.  Predeployment validation of fault-tolerant systems through software-implemented fault insertion , 1989 .

[12]  Jacob A. Abraham,et al.  FAULT CHARACTERIZATION OF VLSI MOS CIRCUITS. , 1982 .

[13]  M. Sytrzycki,et al.  Modeling of gate oxide shorts in MOS transistors , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  J.A. Abraham,et al.  Fault and error models for VLSI , 1986, Proceedings of the IEEE.

[15]  Michael Nicolaidis Shorts in self-checking circuits , 1991, J. Electron. Test..