Error rate estimation of a design implemented in an FPGA based on the operating conditions

This paper presents a framework to evaluate the error rate of a design implemented in an FPGA, depending on the operating conditions. The effects of the operating temperature as well as voltage variation are taken into account. For example, in applications such as the electric vehicle motor control, the non-negligible electromagnetic field can result in FPGA supply voltage variation. It is shown that successfully passing the standard static timing analysis for such an application is not always sufficient to ensure the reliability of the application. Thus, it is needed to assess the operation of the design in the real operating conditions, to ensure the correct execution of the application. The error rate results obtained by measurements show good correlation with the ones obtained from the proposed framework.

[1]  Enrico Macii,et al.  Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  F. F. Sellers,et al.  Analyzing Errors with the Boolean Difference , 1968, IEEE Transactions on Computers.

[3]  Olivier Romain,et al.  Influence of high-power electric motor on an FPGA used in the drive system of electric car , 2016, IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society.

[4]  Shohaib Aboobacker RAZOR: circuit-level correction of timing errors for low-power operation , 2011 .

[5]  Yiorgos Tsiatouhas,et al.  The Time Dilation Technique for Timing Error Tolerance , 2014, IEEE Transactions on Computers.

[6]  João Paulo Teixeira,et al.  Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits , 2012, J. Electron. Test..

[7]  Wayne Luk,et al.  Dynamic voltage scaling for commercial FPGAs , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[8]  Jie Zhang,et al.  ForTER: A forward error correction scheme for timing error resilience , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Robert C. Aitken,et al.  Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience , 2014, IEEE Transactions on Computers.