Codedesign und Hardwarearchitektur für LDPC-Dekodierer mit hohem Durchsatz

[1]  M. Rupp,et al.  Implementation of an LDPC decoder on a vector signal processor , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

[2]  Amir H. Banihashemi,et al.  On implementation of min-sum algorithm for decoding low-density parity-check (LDPC) codes , 2002, Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.

[3]  M.M. Mansour,et al.  Unified decoder architectures for repeat-accumulate and LDPC codes , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

[4]  Frank Kienle,et al.  A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding , 2006, 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications.