Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

[1]  Qiuting Huang,et al.  A 25-MS/s 14-b 200-mW /spl Sigma//spl Delta/ Modulator in 0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[2]  G.C. Temes,et al.  A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC , 2008, IEEE Journal of Solid-State Circuits.

[3]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[4]  Franco Maloberti,et al.  A 5.4mW 2-Channel Time-Interleaved Multi-bit /spl Delta//spl Sigma/ Modulator with 80dB SNR and 85dB DR for ADSL , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[5]  M.H. Perrott,et al.  A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.

[6]  Robert H. M. van Veldhoven,et al.  An Inverter-Based Hybrid ΔΣ Modulator , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  Joseph F. Jensen,et al.  Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators , 2001 .

[8]  T. Tille,et al.  A 0.7-V MOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator in standard digital CMOS technology , 2002 .

[9]  J. Paramesh,et al.  An 11-Bit 330MHz 8X OSR /spl Sigma/-spl Delta/ Modulator for Next-Generation WLAN , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[10]  B. Widrow.  A Study of Rough Amplitude Quantization by Means of Nyquist Sampling Theory , 1956 .

[11]  Shanthi Pavan,et al.  Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Maurits Ortmanns,et al.  Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Lucien Breems,et al.  Continuous-Time Sigma-Delta Modulation for IF A/D Conversion in Radio Receivers , 2001 .

[14]  O. Oliaei.  State-space analysis of clock jitter in continuous-time oversampling data converters , 2003 .

[15]  Shanthi Pavan,et al.  Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  Franco Maloberti,et al.  TOSCA: a simulator for switched-capacitor noise-shaping A/D converters , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Bernhard E. Boser,et al.  The Design of Sigma-Delta Modulation Analog-to-Digit a 1 Converters , 2004 .

[18]  A. Sripad,et al.  A necessary and sufficient condition for quantization errors to be uniform and white , 1977 .

[19]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[20]  F. P. Dawson,et al.  A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR , 2008, IEEE J. Solid State Circuits.

[21]  Hai Tao,et al.  A 400-Ms/s Frequency Translating , 1999 .

[22]  J. Candy,et al.  The Structure of Quantization Noise from Sigma-Delta Modulation , 1981 .

[23]  David J. Allstot,et al.  An 11-bit 330MHz 8X OSR Σ−∆ Modulator for Next-Generation WLAN , 2006 .

[24]  C. S. Petrie,et al.  A multibit sigma-delta ADC for multimode receivers , 2003, IEEE J. Solid State Circuits.

[25]  Francisco V. Fernández,et al.  High-Level Synthesis of Switched-Capacitor , Switched-Current and Continuous-Time Modulators Using SIMULINK-Based Time-Domain Behavioral Models , 2005 .

[26]  Kong-Pang Pun,et al.  A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC , 2007, IEEE Journal of Solid-State Circuits.

[27]  Maurits Ortmanns,et al.  A configurable cascaded continuous-time ΔΣ modulator with up to 15MHz bandwidth , 2010, 2010 Proceedings of ESSCIRC.

[28]  Richard Schreier,et al.  Bandpass sigma-delta modulation , 1989 .

[29]  Andreas Wiesbauer,et al.  A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $\Sigma\Delta$ ADC Based on a Time Encoding Quantizer in 0.13 $\mu$, 2009, IEEE Journal of Solid-State Circuits.

[30]  Gabor C. Temes,et al.  Analog Circuit Design for ADCs , 1997 .

[31]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[32]  J. Huijsing,et al.  A 1.8-mW CMOS /spl Sigma//spl Delta/ modulator with integrated mixer for A/D conversion of IF signals , 2000, IEEE Journal of Solid-State Circuits.

[33]  Bruce A. Wooley,et al.  The Design of Low-Voltage, Low-Power Sigma-Delta Modulators , 1998 .

[34]  R. T. Baird,et al.  Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging , 1995 .

[35]  F. Maloberti,et al.  A low-power multi-bit /spl Sigma//spl Delta/ modulator in 90-nm digital CMOS without DEM , 2005, IEEE Journal of Solid-State Circuits.

[36]  Ngai Wong,et al.  Design of hybrid continuous-time discrete-time delta-sigma modulators , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[37]  Franco Maloberti,et al.  A Low-Power Multi-Bit Modulator in 90-nm Digital CMOS Without , 2005 .

[38]  Robert H. M. van Veldhoven,et al.  A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band , 2007, IEEE Journal of Solid-State Circuits.

[39]  Ian Galton,et al.  Delta-sigma data conversion in wireless transceivers , 2002 .

[40]  Atsushi Iwata,et al.  A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping , 1987 .

[41]  Maurits Ortmanns,et al.  A Method for the Discrete-Time Simulation of Continuous-Time Sigma-Delta Modulators , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[42]  Jurgen van Engelen,et al.  Bandpass Sigma Delta Modulators , 1999 .

[43]  Robert H. M. van Veldhoven,et al.  A 3 . 3-mW Modulator for UMTS in 0 . 18-m CMOS With 70-dB Dynamic Range in 2-MHz Bandwidth , 2009 .

[44]  J. H. Fischer.  Noise sources and calculation techniques for switched capacitor filters , 1982 .

[45]  P. Benabes,et al.  New high-order universal ΣΔ modulator , 1995 .

[46]  Kathleen Philips,et al.  A continuous-time ΣΔ ADC with increased immunity to interferers , 2004 .

[47]  W. Martin Snelgrove,et al.  Continuous-time delta-sigma modulators for high-speed a/d conversion , 2013 .

[48]  Borivoje Nikolic,et al.  A highly reconfigurable 400–1700MHz receiver using a down-converting sigma-delta A/D with 59-dB SNR and 57-dB SFDR over 4-MHz bandwidth , 2009, 2009 Symposium on VLSI Circuits.

[49]  Andrea Baschirotto,et al.  Modeling sigma-delta modulator non-idealities in SIMULINK(R) , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[50]  Eric Andre,et al.  3.3 A 1.2-V Dual-Mode WCDMA/GPRS Σ∆ Modulator , 2003 .

[51]  Chao-Cheng Lee,et al.  An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[52]  P. Fontaine,et al.  A low-noise low-voltage CT /spl Delta//spl Sigma/ modulator with digital compensation of excess loop delay , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[53]  Gabor C. Temes,et al.  Stability Theory for Modulators , 1997 .

[54]  Joseph Mitola,et al.  The software radio architecture , 1995, IEEE Commun. Mag..

[55]  Robert H. Walden,et al.  Analog-to-digital converter survey and analysis , 1999, IEEE J. Sel. Areas Commun..

[56]  Belén Pérez-Verdú,et al.  Bandpass Sigma-Delta A/D Converters: Fundamentals, Architectures and Circuits , 2003 .

[57]  A. Morgado,et al.  A new cascade ΣΔ modulator for low-voltage wideband applications , 2002 .

[58]  Koichi Hamashita,et al.  LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators , 2010, IEEE Journal of Solid-State Circuits.

[59]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[60]  Richard Schreier,et al.  A 375-mW quadrature bandpass ΔΣ ADC with 8.5-MHz BW and 90-dB DR at 44 MHz , 2006 .

[61]  Yi-Gyeong Kim,et al.  A 0.9-V 60-$\mu{\hbox {W}}$ 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range , 2008, IEEE Journal of Solid-State Circuits.

[62]  N. Tan,et al.  Fourth-order two-stage delta-sigma modulator using both 1 bit and multibit quantisers , 1993 .

[63]  M. Conta,et al.  A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[64]  Gabor C. Temes,et al.  Sturdy MASH - modulator , 2006 .

[65]  H. Tao,et al.  Analysis of timing jitter in bandpass sigma-delta modulators , 1999 .

[66]  James C. CAhY.  A Use of Double Integration in Sigma Delta Modulation , 1985 .

[67]  Vinita Vasudevan.  Analysis of Clock Jitter in Continuous-Time Sigma–Delta Modulators , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[68]  R. Schreier,et al.  Noise-shaped multbit D/A convertor employing unit elements , 1995 .

[69]  Maurits Ortmanns,et al.  Continuous time sigma-delta A/D conversion : fundamentals, performance limits and robust implementations , 2006 .

[70]  D.A. Johns,et al.  A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth , 2006, IEEE Journal of Solid-State Circuits.

[71]  Bruce A. Wooley,et al.  A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator , 2008, VLSIC 2008.

[72]  Gabor C. Temes,et al.  Digital correlation technique for the estimation and correction of DAC errors in multibit mash /spl Delta//spl Sigma/ ADCs , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[73]  R.H.M. van Veldhoven.  A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003 .

[74]  Yannis Tsividis,et al.  Integrated continuous-time filter design - an overview , 1994, IEEE J. Solid State Circuits.

[75]  B. Bakkaloglu,et al.  Adaptive Blocker Rejection Continuous-Time $\Sigma \Delta $ ADC for Mobile WiMAX Applications , 2009, IEEE Journal of Solid-State Circuits.

[76]  A. Hairapetian,et al.  An 81 MHz IF receiver in CMOS , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[77]  Sebastian Hoyos,et al.  A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth , 2010, IEEE Journal of Solid-State Circuits.

[78]  Michiel Steyaert,et al.  Erratum to "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS" , 2009, IEEE J. Solid State Circuits.

[79]  Boris Murmann,et al.  A/D converter trends: Power dissipation, scaling and digitally assisted architectures , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[80]  Yves Rolain,et al.  Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS , 2010, IEEE Journal of Solid-State Circuits.

[81]  T. Yamamoto,et al.  A 63 mA 112/94 dB DR IF Bandpass $\Delta\Sigma$ Modulator With Direct Feed-Forward Compensation and Double Sampling , 2008, IEEE Journal of Solid-State Circuits.

[82]  B. Wooley,et al.  A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS , 1997, IEEE J. Solid State Circuits.

[83]  Qiuting Huang,et al.  A 0.13µm CMOS 0.1–20MHz bandwidth 86–70dB DR multi-mode DT ΔΣ ADC for IMT-Advanced , 2010, 2010 Proceedings of ESSCIRC.

[84]  Maurits Ortmanns,et al.  Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[85]  Michael H. Perrott,et al.  A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time � ADC With VCO-Based Integrator and Quantizer Implemented in 0 . 13 � m CMOS , 2009 .

[86]  P. Benabes,et al.  New wideband sigma-delta convertor , 1993 .

[87]  A.H.M. van Roermund,et al.  A continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to interferers , 2004, IEEE Journal of Solid-State Circuits.

[88]  Ian Galton,et al.  Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters , 2001 .

[89]  Youngcheol Chae,et al.  Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator , 2009, IEEE Journal of Solid-State Circuits.

[90]  R. Schreier,et al.  A 375-mW Quadrature Bandpass $\Delta\Sigma$ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz , 2006, IEEE Journal of Solid-State Circuits.

[91]  B. M. Putter,et al.  /spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[92]  Omid Shoaei,et al.  Continuous-Time Delta-Sigma A/D Converters for High Speed Applications , 1995 .

[93]  Un-Ku Moon,et al.  Multi-loop efficient sturdy MASH delta-sigma modulators , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[94]  Y. Watanabe,et al.  A 1.2V 3.5mW /spl Delta//spl Sigma/ modulator with a passive current summing network and a variable gain function , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[95]  Georges G. E. Gielen,et al.  Analyzing continuous-time /spl Delta//spl Sigma/ Modulators with generic behavioral models , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[96]  Richard Gaggl,et al.  A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-μm CMOS , 2003, IEEE J. Solid State Circuits.

[97]  Ralf Wunderlich,et al.  A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $\mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.

[98]  Gabor C. Temes,et al.  Oversampling delta-sigma data converters : theory, design, and simulation , 1992 .

[99]  M.Z. Straayer,et al.  A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, IEEE Journal of Solid-State Circuits.

[100]  Andreas Wiesbauer,et al.  Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[101]  E. Sánchez-Sinencio,et al.  A Continuous-Time Modulator With 88-dB Dynamic Range and 1 . 1-MHz Signal Bandwidth , 2001 .

[102]  W. Sansen,et al.  A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[103]  J. M. Khoury,et al.  A 400-Ms/s frequency translating bandpass sigma-delta modulator , 1999, IEEE J. Solid State Circuits.

[104]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[105]  Gabor C. Temes,et al.  Multibit sigma-delta modulator with reduced sensitivity to DAC nonlinearity , 1991 .

[106]  W. Snelgrove,et al.  Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .

[107]  M. Clara,et al.  A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution , 2004, IEEE Journal of Solid-State Circuits.

[108]  Yong Ping Xu,et al.  Multibit Delta-Sigma Modulator With Noise-Shaping Dynamic Element Matching , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[109]  Ian Galton,et al.  A mostly digital variable-rate continuous-time ADC ΔΣ modulator , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[110]  W. R. Bennett,et al.  Spectra of quantized signals , 1948, Bell Syst. Tech. J..

[111]  Bruce A. Wooley,et al.  A 0.7-V 870- W Digital-Audio CMOS , 2009 .

[112]  E.J. van der Zwan,et al.  A 0.2 mW CMOS /spl Sigma//spl Delta/ modulator for speech coding with 80 dB dynamic range , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[113]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[114]  K. Nguyen,et al.  A 106dB SNR hybrid oversampling ADC for digital audio , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[115]  S. Jantzi,et al.  A fourth-order bandpass sigma-delta modulator , 1993 .

[116]  Shanthi Pavan,et al.  Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique , 2010, IEEE Journal of Solid-State Circuits.

[117]  A.H.M. van Roermund,et al.  Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer , 2006, IEEE Journal of Solid-State Circuits.

[118]  Á. Rodríguez-Vázquez,et al.  A New High-Level Synthesis Methodology of Cascaded Continuous-Time Modulators , 2006 .

[119]  Chen Lei.  Modeling Sigma-delta Modulator Non-Idealities in SIMULINK , 2008 .

[120]  Mohamad Sawan,et al.  On the Design of Undersampling Continuous-Time Bandpass Delta–Sigma Modulators for Gigahertz Frequency A/D Conversion , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[121]  Shanthi Pavan.  Systematic Design Centering of Continuous Time Oversampling Converters , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[122]  Andreas Wiesbauer,et al.  Exploiting time resolution in nanometre CMOS data converters , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[123]  Ian Galton,et al.  A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[124]  K.C.-H. Chao,et al.  A higher order topology for interpolative modulators for oversampling A/D converters , 1990 .

[125]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[126]  Thomas Blon,et al.  A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .

[127]  Shen-Iuan Liu,et al.  A Fully Differential Comparator-Based Switched-Capacitor $\Delta\Sigma$ Modulator , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[128]  M. S. Kappes,et al.  A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications , 2003, IEEE J. Solid State Circuits.

[129]  Ángel Rodríguez-Vázquez,et al.  High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[130]  William Martin Snelgrove,et al.  A 950-MHz IF second-order integrated LC bandpass delta-sigma modulator , 1998 .

[131]  R. V. Veldhoven.  A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.

[132]  Michael H. Perrott,et al.  A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, VLSIC 2008.

[133]  Shanthi Pavan,et al.  Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta–Sigma Modulators , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[134]  Bang-Sup Song,et al.  A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[135]  J.R. Long,et al.  Adaptive multi-standard circuits and systems for wireless communications , 2006, IEEE Circuits and Systems Magazine.

[136]  L. R. Carley,et al.  Simulation of Delta - Sigma modulators using behavioral models , 1990, IEEE International Symposium on Circuits and Systems.

[137]  T. C. Leslie,et al.  An improved sigma-delta modulator architecture , 1990, IEEE International Symposium on Circuits and Systems.

[138]  Georges G. E. Gielen,et al.  A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[139]  Michiel Steyaert,et al.  Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS , 2006 .

[140]  Bernard Mulgrew,et al.  On the design of high-performance wide-band continuous-time sigma-delta converters using numerical optimization , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[141]  Francisco V. Fernández,et al.  A New High-Level Synthesis Methodology of Cascaded Continuous-Time$SigmaDelta$Modulators , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[142]  Georges G. E. Gielen,et al.  An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[143]  Cram,et al.  Discrete-time signal processing : Alan V. Oppenheim, 3rd edition , 2011 .

[144]  Van Der Zwan.  A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range , 1996 .

[145]  Gabor C. Temes,et al.  Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization , 1996, Proc. IEEE.

[146]  Yoshihisa Fujimoto,et al.  A 100 MS/s 4 MHz Bandwidth 70 dB SNR $\Delta \Sigma$ ADC in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[147]  Michiel Steyaert,et al.  Design of low-voltage low-power CMOS delta-sigma A/D converters , 1999 .

[148]  Enrique Prefasi,et al.  A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[149]  Edgar Sánchez-Sinencio,et al.  A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[150]  Enrique Prefasi,et al.  Analog-to-digital conversion using noise shaping and time encoding , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[151]  B. A. Wooley,et al.  A 1.8-V digital-audio sigma-delta modulator in 0.8-/spl mu/m CMOS , 1997 .

[152]  A. Torralba,et al.  A 4.7mW 89.5dB DR CT complex /spl Delta//spl Sigma/ ADC with built-in LPF , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[153]  Thomas Burger,et al.  A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD , 2007, ISSCC.

[154]  William Martin Snelgrove,et al.  Switched-capacitor bandpass delta-sigma A/D modulation at 10.7 MHz , 1995, IEEE J. Solid State Circuits.

[155]  Ian Galton,et al.  Segmented mismatch-shaping D/A conversion , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[156]  H. Inose,et al.  A Telemetering System by Code Modulation - Δ- ΣModulation , 1962, IRE Transactions on Space Electronics and Telemetry.

[157]  Richard Schreier,et al.  Bandpass sigma-delta analog-to-digital conversion , 1991 .

[158]  Gabor C. Temes,et al.  DeltaSigma ADCs with Multibit Internal Converters , 1997 .

[159]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[160]  Michiel Steyaert,et al.  A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS , 2010, IEEE Journal of Solid-State Circuits.

[161]  Michiel Steyaert,et al.  Design of Multi-Bit Delta-SIGMA A/D Converters , 2002 .

[162]  E. Sanchez-Sinencio,et al.  A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[163]  R. Schreier.  On the use of chaos to reduce idle-channel tones in delta-sigma modulators , 1994 .

[164]  Shanthi Pavan.  Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[165]  Bas M. Putter.  A 5,sup>th-order CT/DT Multi-Mode ΔΣ Modulator , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[166]  Maurits Ortmanns,et al.  A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator , 2003 .

[167]  Maurits Ortmanns,et al.  A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[168]  Mohammad Ranjbar,et al.  A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA , 2010, IEEE Journal of Solid-State Circuits.

[169]  B.A. Wooley,et al.  A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator , 2008, IEEE Journal of Solid-State Circuits.

[170]  F. Kuttner,et al.  10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 /spl mu/m CMOS process , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[171]  J.H. Huijsing,et al.  An IF-to-Baseband $\Sigma \Delta$ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range , 2007, IEEE Journal of Solid-State Circuits.

[172]  Jonathan Borremans,et al.  A 2.4 GHz Low-Power Sixth-Order RF Bandpass $\Delta\Sigma$ Converter in CMOS , 2009, IEEE Journal of Solid-State Circuits.

[173]  H. V. Sorensen,et al.  An overview of sigma-delta converters , 1996, IEEE Signal Process. Mag..

[174]  John J. Paulos,et al.  An analysis of nonlinear behavior in delta-sigma modulators , 1987 .

[175]  J. Roh,et al.  A 0 . 9V 60-� W 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range , 2008 .

[176]  Bruce A. Wooley,et al.  A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion , 1991 .

[177]  Jinseok Koh,et al.  A 66dB DR 1.2V 1.2mW single-amplifier double-sampling 2/sup nd/-order /spl Delta//spl Sigma/ ADC for WCDMA in 90nm CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[178]  E. Riccio,et al.  A 3mW continuous-time /spl Sigma//spl Delta/-modulator for EDGE/GSM with high adjacent channel tolerance , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[179]  Lars Sundström,et al.  Design and Measurement of a CT � ADC With Switched-Capacitor Switched-Resistor Feedback , 2009 .

[180]  Yannis Tsividis,et al.  Integrated continuous-time filter design , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[181]  B. Bakkaloglu,et al.  A 1.5V 1mA 80dB passive /spl Sigma//spl Delta/ ADC in 0.13/spl mu/m digital CMOS process , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[182]  Georges Gielen,et al.  CAD tools for data converter design: an overview , 1996 .

[183]  Ian Galton.  Spectral shaping of circuit errors in digital-to-analog converters , 1997 .

[184]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[185]  Akira Matsuzawa,et al.  A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator , 2010, IEEE Journal of Solid-State Circuits.

[186]  Patrizia Greco,et al.  A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS , 2005 .

[187]  F. Kuttner,et al.  A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS , 2005, IEEE Journal of Solid-State Circuits.

[188]  J. M. de la Rosa,et al.  Cascade ΣΔ modulator for low-voltage wideband applications , 2007 .

[189]  Johan H. Huijsing,et al.  A 1.8-mW CMOS sigma delta modulator with integrated mixer for A/D conversion of IF signals , 2000 .

[190]  Krishnamurthy Soumyanath,et al.  A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[191]  Shanthi Pavan,et al.  A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications , 2008, IEEE Journal of Solid-State Circuits.

[192]  K. Philips,et al.  A 4.4mW 76dB complex /spl Sigma//spl Delta/ ADC for Bluetooth receivers , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[193]  Franco Maloberti,et al.  3.4 A 14mW Multi-bit ∆Σ Modulator with 82dB SNR and 86dB DR for ADSL2+ , 2006 .

[194]  Robert M. Gray,et al.  Quantization noise spectra , 1990, IEEE Trans. Inf. Theory.

[195]  W. Snelgrove,et al.  Excess loop delay in continuous-time delta-sigma modulators , 1999 .

[196]  Andreas Wiesbauer,et al.  Modulator for ADSL CO Applications , 2004 .

[197]  Lars Sundström,et al.  Design and Measurement of a CT $\Delta\Sigma$ ADC With Switched-Capacitor Switched-Resistor Feedback , 2009, IEEE Journal of Solid-State Circuits.

[198]  R. Castello,et al.  Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end , 2006, IEEE Circuits and Systems Magazine.

[199]  F. Maloberti,et al.  A mirror image free two-path bandpass /spl Sigma//spl Delta/ modulator with 72 dB SNR and 86 dB SFDR , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).