A modular 0.7 mu m CMOS JESSI test chip for multi purpose applications

A CMOS 0.7- mu m test chip for technology and model parameter measurements and reliability testing is presented. The basic concept is based on well-defined standardized modules with fixed sizes. It was designed by eight European companies with common JESSI (Joint European Submicron Silicon) design rules. The focus was on high-frequency test structures and connections for highly accurate on-wafer measurements and deembedding methods over a wide frequency range.<<ETX>>

[1]  G. J. Wipfler,et al.  Model parameter generation for high-performance circuit simulation , 1989, Proceedings. VLSI and Computer Peripherals. COMPEURO 89.

[2]  H. Schinagel,et al.  Test structures and measurement techniques for the characterization of the dynamic behaviour of CMOS transistors on wafer in the GHz range , 1992, ICMTS 92 Proceedings of the 1992 International Conference on Microelectronic Test Structures.

[3]  H. Richter,et al.  A new method and test structure for easy determination of femto-farad on-chip capacitances in a MOS process , 1992, ICMTS 92 Proceedings of the 1992 International Conference on Microelectronic Test Structures.