ODC 클록 게이팅을 이용한 저전력 DATA PATH 설계

In this paper, a sample design of Data Path using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. Using modified this value, this paper shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce dynamic power reductions of around 40%.