Side-Channel Analysis Protection and Low-Latency in Action - - Case Study of PRINCE and Midori -

During the last years, the industry sector showed particular interest in solutions which allow to encrypt and decrypt data within one clock cycle. Known as low-latency cryptography, such ciphers are desirable for pervasive applications with real-time security requirements. On the other hand, pervasive applications are very likely in control of the end user, and may operate in a hostile environment. Hence, in such scenarios it is necessary to provide security against side-channel analysis (SCA) attacks while still keeping the low-latency feature.

[1]  Alessandro Barenghi,et al.  On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs , 2011, CCS '11.

[2]  Thomas Eisenbarth,et al.  Simpler, Faster, and More Robust T-Test Based Leakage Detection , 2016, COSADE.

[3]  Christof Paar,et al.  Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World , 2011, CHES.

[4]  Sylvain Guilley,et al.  Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks , 2010, CT-RSA.

[5]  Christof Paar,et al.  On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoqCode Hopping Scheme , 2008, CRYPTO.

[6]  Ventzislav Nikov,et al.  Low-Latency Encryption - Is "Lightweight = Light + Wait"? , 2012, CHES.

[7]  Amir Moradi,et al.  Assessment of Hiding the Higher-Order Leakages in Hardware - What Are the Achievements Versus Overheads? , 2015, CHES.

[8]  P. Rohatgi,et al.  A testing methodology for side channel resistance , 2011 .

[9]  David L. Dill,et al.  Efficient self-timing with level-encoded 2-phase dual-rail (LEDR) , 1991 .

[10]  Yong-Bin Kim,et al.  Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems , 2010, GLSVLSI '10.

[11]  David S. Brée,et al.  A clock-less implementation of the AES resists to power and timing attacks , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[12]  Sylvain Guilley,et al.  Countering early evaluation: an approach towards robust dual-rail precharge logic , 2010, WESS '10.

[13]  Gilles Sicard,et al.  Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals , 2005, VLSI-SoC.

[14]  Amir Moradi,et al.  Leakage Assessment Methodology - A Clear Roadmap for Side-Channel Evaluations , 2015, CHES.

[15]  Wei Sun,et al.  Small Tweaks Do Not Help: Differential Power Analysis of MILENAGE Implementations in 3G/4G USIM Cards , 2015, ESORICS.

[16]  Kiyoshi Oguri,et al.  Asynchronous Circuit Design , 2001 .

[17]  François Durvaux,et al.  Towards Easy Leakage Certification , 2016, CHES.

[18]  François Durvaux,et al.  From Improved Leakage Detection to the Detection of Points of Interests in Leakage Traces , 2016, EUROCRYPT.

[19]  Christof Paar,et al.  Practical evaluation of DPA countermeasures on reconfigurable hardware , 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

[20]  Bogdanov Andrey,et al.  Midori: A Block Cipher for Low Energy , 2016 .

[21]  Akashi Satoh,et al.  Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card , 2015, 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE).

[22]  Luis A. Plana,et al.  An investigation into the security of self-timed circuits , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[23]  Daisuke Suzuki,et al.  Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style , 2006, CHES.

[24]  Axel Poschmann,et al.  Lightweight cryptography: cryptographic engineering for a pervasive world , 2009, IACR Cryptol. ePrint Arch..

[25]  Bart Preneel,et al.  Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? , 2004, CHES.

[26]  George S. Taylor,et al.  Security Evaluation of Asynchronous Circuits , 2003, CHES.

[27]  Anne Canteaut,et al.  PRINCE - A Low-Latency Block Cipher for Pervasive Computing Applications - Extended Abstract , 2012, ASIACRYPT.

[28]  Vincent Rijmen,et al.  Higher-Order Threshold Implementations , 2014, ASIACRYPT.

[29]  Jean-Jacques Quisquater,et al.  On the Need of Physical Security for Small Embedded Devices: A Case Study with COMP128-1 Implementations in SIM Cards , 2013, Financial Cryptography.

[30]  Ingrid Verbauwhede,et al.  A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[31]  Vincent Rijmen,et al.  Threshold implementations of small S-boxes , 2014, Cryptography and Communications.

[32]  Christof Paar,et al.  Pushing the Limits: A Very Compact and a Threshold Implementation of AES , 2011, EUROCRYPT.

[33]  M. Renaudin,et al.  A clock-less low-voltage AES crypto-processor , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[34]  Marc Renaudin,et al.  DPA on quasi delay insensitive asynchronous circuits: formalization and improvement , 2005, Design, Automation and Test in Europe.

[35]  Paul C. Kocher,et al.  Differential Power Analysis , 1999, CRYPTO.

[36]  Vincent Rijmen,et al.  Threshold Implementations of all 3x3 and 4x4 S-boxes , 2012, IACR Cryptol. ePrint Arch..

[37]  Gilles Sicard,et al.  Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits , 2006, CHES.

[38]  Syed Kareem Uddin.  Trade-OFFS For Threshold Implementations Illustrated on AES , 2017 .

[39]  Naofumi Homma,et al.  Improved Power Analysis on Unrolled Architecture and Its Application to PRINCE Block Cipher , 2015, LightSec.

[40]  Matthew J. B. Robshaw,et al.  PRINTcipher: A Block Cipher for IC-Printing , 2010, CHES.

[41]  Ingrid Verbauwhede,et al.  Power Analysis of Atmel CryptoMemory - Recovering Keys from Secure EEPROMs , 2012, CT-RSA.

[42]  Yu Sasaki,et al.  Invariant Subspace Attack Against Full Midori64 , 2015, IACR Cryptol. ePrint Arch..

[43]  P. Rohatgi,et al.  Test Vector Leakage Assessment ( TVLA ) methodology in practice , 2013 .

[44]  Joe Kilian,et al.  How to Protect DES Against Exhaustive Key Search , 1996, CRYPTO.

[45]  Andrey Bogdanov,et al.  Exploring Energy Efficiency of Lightweight Block Ciphers , 2015, IACR Cryptol. ePrint Arch..

[46]  Stefan Mangard,et al.  Power analysis attacks - revealing the secrets of smart cards , 2007 .

[47]  George S. Taylor,et al.  Improving smart card security using self-timed circuits , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[48]  Vincent Rijmen,et al.  Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches , 2011, Journal of Cryptology.

[49]  Mark G. Karpovsky,et al.  Delay insensitive encoding and power analysis: a balancing act [cryptographic hardware protection] , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[50]  Andrey Bogdanov,et al.  PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.

[51]  V. Neelima,et al.  A More Efficient AES Threshold Implementation , 2016 .

[52]  Amir Moradi,et al.  Early Propagation and Imbalanced Routing, How to Diminish in FPGAs , 2014, IACR Cryptol. ePrint Arch..

[53]  Amir Moradi,et al.  Side-Channel Resistant Crypto for Less than 2,300 GE , 2011, Journal of Cryptology.

[54]  Steve Furber,et al.  Principles of Asynchronous Circuit Design: A Systems Perspective , 2010 .