ON-CHIP DEBUG ARCHITECTURES FOR IMPROVING OBSERVABILITY DURING POST-SILICON VALIDATION

Post-silicon validation has become an essential step in the design flow of system-onchip devices for the purpose of identifying and fixing design errors that have escaped pre-silicon verification. To address the limited observability of the circuits during post-silicon validation, embedded logic analysis techniques are employed in order to probe the internal circuit nodes at-speed and in real-time. In this dissertation, we propose novel on-chip debug architectures and the associated debug methods, which improve observability during at-speed post-silicon validation. First, we propose a novel embedded debug architecture that enables real-time lossless data compression in order to extend the observation window of a debug experiment. The proposed architecture is particularly suitable for in-field debugging on application boards that have sources of non-deterministic behavior, such as asynchronous interfaces. To quantify the performance gain from using lossless compression in embedded logic analysis, we present a new compression ratio metric that captures the trade-off between the area overhead and the increase in the observation window. Second, we propose a novel architecture based on lossy compression. This architecture enables a new debug method where the designer can iteratively zoom only in the intervals that contain erroneous samples. Thus, it is tailored for the identification of the hard-to-detect functional bugs that occur intermittently over a long execution time. When compared to increasing the size of the trace buffer, the proposed architecture has a small impact on silicon area, while significantly reducing the number of debug sessions. The new debug method is applicable to both automatic test equipment-based debugging, as well as in-field debugging on application boards, so long as the debug experiment can be reproduced synchronously.