Efficient hardware architecture of deterministic MPA decoder for SCMA

Sparse code multiple access (SCMA) is a new kind of multiple access (MA) technology which ranks one of the most promising candidates for 5G wireless because of its outstanding performance. SCMA enjoys stronger overloading tolerance compared with traditional MA technologies. It also takes the advantage of sparse property to achieve lower complexity when using message passing algorithm (MPA). In this paper, a deterministic MPA (DMAP) is proposed for SCMA. Numerical result shows that DMPA achieves good performance in term of bit error rate (BER) and is capable to transmit more information with the same amount of physical resources. Furthermore, hardware architecture of DMPA is also put forward in this paper. For original DMPA, the data is updated in single but bulky step, which slows down the operation frequency. Apart from this, the DMPA decoder has 4 basic units, in need of large amount of hardware. Therefore, a stage-level folded structure for DMPA is first proposed with consideration of both the speed and efficiency, which is the main contribution. For better demonstration of the advantages, a loop bound analysis of it has also been made in this paper.