An On-Chip Power Supply Regulator to Reduce the Switching Noise

In a synchronous clock-distribution network of typi cal automotive chips, digital circuits switch simultaneously on the clock edge; therefore, they generate high-switching (or di/dt) noise on the power supply lines due to sharp peaks of the supply cur rent, which is the source for electromagnetic emissions (EME). In this paper, we demonstrate an effective combination of two design techniques for di/dt noise reduction based on the supply current-shaping technique: 1) introducing an EME-suppressing regulator (EME-SR) with a digital feedback loop and 2) FM of the discrete-time EME-SR's clock. The former technique reduces the time-domain peaks as well as the spectral power of the supply cur rent by a discrete-time EME-SR and a tank capacitor. The latter technique reduces the peak spectral power of the supply current by spreading this power into the sidelobes.

[1]  Raj Mittra,et al.  Electromagnetic interference mitigation by using a spread-spectrum approach , 2002 .

[2]  Masashi Horiguchi,et al.  A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier , 1990 .

[3]  T. Ohsawa,et al.  A new on-chip converter for submicrometer high-density DRAMs , 1987 .

[4]  Wim Dehaene,et al.  Design of an on-chip EMI-suppressing regulator for automotive electronics applications , 2007 .

[5]  David J. Allstot,et al.  Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs , 1993 .

[6]  Keith Bryan Hardin,et al.  Spread spectrum clock generation for the reduction of radiated emissions , 1994, Proceedings of IEEE Symposium on Electromagnetic Compatibility.

[7]  David J. Allstot,et al.  CMOS current steering logic for low-voltage mixed-signal integrated circuits , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Wim Dehaene,et al.  Comparison of logic families for improved EMC behavior of mixed signal Ics , 2005, EMC 2005.

[9]  T. Sudo.  Behavior of switching noise and electromagnetic radiation in relation to package properties and on-chip decoupling capacitance , 2006, 2006 17th International Zurich Symposium on Electromagnetic Compatibility.

[10]  Mark Ingels,et al.  Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's , 1997 .

[11]  W. Dehaene,et al.  A fully integrated low EMI noise power supply technique for CMOS digital IC’s in automotive applications , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[12]  Wim Dehaene,et al.  Measurements of an EMC test chip for lower EME in CMOS digital ICs , 2008 .

[13]  Patrik Larsson,et al.  di/dt Noise in CMOS Integrated Circuits , 1997 .

[14]  S. Kiaei,et al.  Analog logic techniques steer around the noise , 1993, IEEE Circuits and Devices Magazine.

[15]  H. De Man,et al.  Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[16]  W. Dehaene,et al.  A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[17]  David J. Allstot,et al.  Synthesis techniques for CMOS folded source-coupled logic circuits , 1992 .

[18]  Y. Oowaki,et al.  Noise suppression scheme for giga-scale DRAM with hundreds of I/Os , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[19]  E. Sicard,et al.  Characterization and modeling of parasitic emission in deep submicron CMOS , 2005, IEEE Transactions on Electromagnetic Compatibility.

[20]  D.J. Allstot,et al.  Current-mode logic techniques for CMOS mixed-mode ASICs , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[21]  Larry D. Smith,et al.  Power distribution system design methodology and capacitor selection for modern CMOS technology , 1999 .

[22]  Yukihito Oowaki,et al.  Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's , 1998 .

[23]  Liwen Huang,et al.  Effects of on-package decoupling on microprocessor power delivery design , 1996 .

[24]  Masaaki Yamada,et al.  EMI-noise analysis under ASIC design environment , 1999, ISPD '99.

[25]  Soo-Hyung Kim,et al.  Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).

[26]  Willy Sansen,et al.  analog design essentials , 2011 .

[27]  J. R. Carson.  Notes on the Theory of Modulation , 1922, Proceedings of the Institute of Radio Engineers.

[28]  W. Sansen.  Challenges in analog IC design submicron CMOS technologies , 1996, 1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings.

[29]  Davide Pandini,et al.  Clock Distribution Techniques for Low-EMI Design , 2007, PATMOS.

[30]  Aarnout Wieers,et al.  METHODOLOGY AND CASE STUDY FOR HIGH IMMUNITY AUTOMOTIVE DESIGN , 2007 .

[31]  Kaushik Roy,et al.  A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[32]  Wim Dehaene,et al.  Evaluation of power supply noise in CMOS and low noise logic cells , 2008, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility.