A 16-levels/cell dynamic memory

A multilevel storage dynamic memory using a standard DRAM memory cell array is presented. A staircase word pulse and a charge-transfer preamplifier are used for converting binary data to multilevel storage voltages and vice versa. The 16-level (4-bit)/cell READ/WRITE operation has been confirmed at storage levels as low as 80-100 mV. The storage-level voltage accuracy is limited basically by subthreshold leakage current.

[1]  R. Merrill,et al.  CCD memory using multilevel storage , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  D.A. Hodges,et al.  Multilevel random-access memory using one transistor per cell , 1976, IEEE Journal of Solid-State Circuits.

[3]  K. Fujishima,et al.  A new multilevel storage structure for high density CCD memory , 1978, IEEE Journal of Solid-State Circuits.

[4]  L. G. Heller,et al.  High sensitivity charge-transfer sense amplifier , 1975 .