Execution-Based Model Checking for High-Level Designs

In this chapter, we present an high-level property checking approach. We begin with a general description of verification of concurrent programs, and then describe it for a high-level language called SystemC [78]. In this approach, we start with a design written in SystemC, and then use model checking techniques to verify that the design satisfies a given property such as the absence of deadlocks or assertion violations.

[1]  Patrice Godefroid,et al.  Model checking for programming languages using VeriSoft , 1997, POPL '97.

[2]  Rajesh Gupta,et al.  Partial order reduction for scalable testing of SystemC TLM designs , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[3]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[4]  Patrice Godefroid,et al.  Dynamic partial-order reduction for model checking software , 2005, POPL '05.

[5]  Ingolf H. Krüger,et al.  Compositional Reactive Semantics of SystemC and Verification with RuleBase , 2007 .

[6]  Todd Millstein,et al.  Automatic predicate abstraction of C programs , 2001, PLDI '01.

[7]  Florence Maraninchi,et al.  Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip , 2006, 2006 Formal Methods in Computer Aided Design.

[8]  Robert K. Brayton,et al.  Partial-Order Reduction in Symbolic State-Space Exploration , 2001, Formal Methods Syst. Des..

[9]  Vineet Kahlon,et al.  Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions , 2006, CAV.

[10]  Stuart Swan,et al.  SystemC transaction level models and RTL verification , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[11]  Florence Maraninchi,et al.  LusSy: a toolbox for the analysis of systems-on-a-chip at the transactional level , 2005, Fifth International Conference on Application of Concurrency to System Design (ACSD'05).

[12]  Vijay K. Garg,et al.  Formal Verification of Simulation Traces Using Computation Slicing , 2007, IEEE Transactions on Computers.

[13]  Thorsten Grotker,et al.  System Design with SystemC , 2002 .

[14]  Orna Grumberg,et al.  Bounded Model Checking of Concurrent Programs , 2005, CAV.

[15]  Patrice Godefroid,et al.  Partial-Order Methods for the Verification of Concurrent Systems , 1996, Lecture Notes in Computer Science.

[16]  David L. Dill,et al.  The Murphi Verification System , 1996, CAV.

[17]  G. Ramalingam,et al.  Context-sensitive synchronization-sensitive analysis is undecidable , 2000, TOPL.

[18]  Daniel Kroening,et al.  Formal verification of SystemC by automatic hardware/software partitioning , 2005, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05..

[19]  Sofiène Tahar,et al.  Design for verification of SystemC transaction level models , 2005, Design, Automation and Test in Europe.

[20]  Matthew B. Dwyer,et al.  Slicing Software for Model Construction , 2000, High. Order Symb. Comput..

[21]  Gerard J. Holzmann,et al.  The Model Checker SPIN , 1997, IEEE Trans. Software Eng..

[22]  Moshe Y. Vardi Formal Techniques for SystemC Verification; Position Paper , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[23]  Milind Girkar,et al.  Automatic Extraction of Functional Parallelism from Ordinary Programs , 1992, IEEE Trans. Parallel Distributed Syst..

[24]  Chao Wang,et al.  Peephole Partial Order Reduction , 2008, TACAS.

[25]  Rolf Drechsler,et al.  Improvements for constraint solving in the systemc verification library , 2007, GLSVLSI '07.

[26]  Aarti Gupta,et al.  Efficient Modeling of Concurrent Systems in BMC , 2008, SPIN.