Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations

This paper presents an efficient yield optimization approach using k-means clustering algorithm to reduce Monte Carlo (MC) simulations. This approach uses a commercial electrical simulator and PDK models for evaluation purposes. The method was integrated in an analog IC design flow that includes the AIDA-C circuit sizing optimization tool. The proposed yield estimation technique reduces the number of required MC simulations during the optimization process. The simulated solutions are the most likely to populate the Pareto optimal front and result from a selection process based on a modified k-means algorithm. The proposed approach leads 75% reduction in the total number of the MC simulations for the presented case study.

[1]  João Goes,et al.  Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners , 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

[2]  Saraju P. Mohanty,et al.  Fast statistical process variation analysis using universal Kriging metamodeling: A PLL example , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

[3]  Jorge Guilherme,et al.  Analog IC Design Automation , 2006 .

[4]  Rob A. Rutenbar,et al.  Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Colin C. McAndrew,et al.  Corner models: Inaccurate at best, and it only gets worst … , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[6]  Georges G. E. Gielen,et al.  Efficient analog circuit synthesis with simultaneous yield and robustness optimization , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[7]  Gunhan Dundar,et al.  Integration of QMC based yield-aware pareto front techniques on MOEA/D for robust analog synthesis , 2015, 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[8]  Ricardo Povoa,et al.  AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation , 2015, 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[9]  J. MacQueen.  Some methods for classification and analysis of multivariate observations , 1967 .

[10]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[11]  Sergei Vassilvitskii,et al.  k-means++: the advantages of careful seeding , 2007, SODA '07.

[12]  Robert Spence,et al.  Tolerance Design of Electronic Circuits , 1997 .