Parallel processing architecture for the Hitachi S-3800 shared-memory vector multiprocessor

This paper discusses the architecture of the new Hitachi supercomputer series, which is capable of achieving 8 GFLOPS in each of up to four processors. This architecture provides high-performance processing for fine-grain parallelism, and it allows efficient parallel processing even in an undedicated environment. It also features the newly-developed time-limited spin-loop synchronization, which combines spin-loop synchronization with operating system primitives, and a communication buffer (CB) which caches shared variables for synchronization, thus allowing them to be accessed faster. Three new instructions take advantage of the CB in order to reduce the parallel overhead. The results of performance measurements confirm the effectiveness of the CB and the new instructions.

[1]  Ralph Grishman,et al.  The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer , 1983, IEEE Transactions on Computers.

[2]  A. Gottleib,et al.  The nyu ultracomputer- designing a mimd shared memory parallel computer , 1983 .

[3]  Richard J. Sahulka,et al.  IBM Parallel FORTRAN , 1988, IBM Syst. J..

[4]  Shigeko Yazawa,et al.  High-Speed Vector Instruction Execution Schemes of HITACHI Supercomputer S-820 System , 1988, ICPP.

[5]  Tom Jones Engineering design of the Convex C2 , 1989, Computer.

[6]  Shun Kawabe,et al.  An Overview of the Hitachi S-3800 Series Supercomputer , 1992, Supercomputer.

[7]  Tadaaki Isobe,et al.  High-speed storage control schemes of HITACHI supercomputer S-820 system , 1989, ICS '89.

[8]  Masakazu Fukagawa,et al.  High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system , 1988, ICS '88.

[9]  Ulrich Detert,et al.  CRAY X-MP and Y-MP memory performance , 1991, Parallel Comput..

[10]  Tadashi Watanabe,et al.  The Parallel Processing Feature of the NEC SX-3 Supercomputer System , 1991, Int. J. High Speed Comput..

[11]  Kevin P. McAuliffe,et al.  The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture , 1985, ICPP.

[12]  Paolo Carnevali,et al.  Microtasking on IBM Multiprocessors , 1986, IBM J. Res. Dev..

[13]  Christopher C. Hsiung,et al.  Cray X-MP: the birth of a supercomputer , 1989, Computer.

[14]  Wilfried Oed Cray Y-MP C90: System features and early benchmark results (Short communication) , 1992, Parallel Comput..

[15]  Kai Hwang,et al.  Computer architecture and parallel processing , 1984, McGraw-Hill Series in computer organization and architecture.