Improving Energy Efficiency by Phase-Grained Migration for Asymmetric Multicore

Asymmetric multicore architecture that consists of multiple cores with different power and performance features has the potential for improving energy efficiency. Migrating threads with different characteristics to appropriate cores can reap the full benefits of the asymmetry to improve energy efficiency. A key challenge in the use of asymmetric processors is to determine the reassignment of threads to asymmetric processor cores according to changing program phases within threads. In this paper we propose a scheme to improve the energy efficiency by phase-grained thread migration for asymmetric multicore. Our scheme mainly includes three new techniques. Firstly, we employ a linear estimation model with high accuracy to directly estimate performance per watt of the current thread phase on each core type online. These information of performance per watt decides the affinities of threads to cores. Secondly, according to the affinities of threads to cores and the overhead of migration, an Energy Efficiency Optimization Model (EEOM) is proposed to clarify the problem of thread-to-core assignment. Lastly, we present a scheduling algorithm based on the Kuhn-Munkres (KM) algorithm to find an optimal solution of the EEOM. We compare our proposed scheme with the state-of-the-art static assignment, and the result shows that our scheme can reach up to 9.5% improvement of performance per watt.

[1]  D. West.  Introduction to Graph Theory , 1995 .

[2]  Manuel Prieto,et al.  A comprehensive scheduler for asymmetric multicore systems , 2010, EuroSys '10.

[3]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[4]  James E. Smith,et al.  Comparing program phase detection techniques , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[5]  Norman P. Jouppi,et al.  Core architecture optimization for heterogeneous chip multiprocessors , 2006, 2006 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[6]  Norman P. Jouppi,et al.  Cacti 3. 0: an integrated cache timing, power, and area model , 2001 .

[7]  Ryan E. Grant,et al.  Power-performance efficiency of asymmetric multiprocessors for multi-threaded scientific applications , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

[8]  Patrick Crowley,et al.  Dynamic thread assignment on heterogeneous multiprocessor architectures , 2006, CF '06.

[9]  Stacey Jeffery,et al.  HASS: a scheduler for heterogeneous multicore systems , 2009, OPSR.

[10]  Koushik Chakraborty,et al.  Computation spreading: employing hardware migration to specialize CMP cores on-the-fly , 2006, ASPLOS XII.

[11]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[12]  Jonathan A. Winter,et al.  Scheduling algorithms for unpredictably heterogeneous CMP architectures , 2008, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).

[13]  Omer Khan,et al.  A self-adaptive scheduler for asymmetric multi-cores , 2010, GLSVLSI '10.

[14]  Margaret Martonosi,et al.  Power prediction for Intel XScale/spl reg/ processors using performance monitoring unit events , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[15]  K. Steinhubl.  Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[16]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[17]  Brad Calder,et al.  Discovering and Exploiting Program Phases , 2003, IEEE Micro.

[18]  Lizy Kurian John,et al.  Efficient program scheduling for heterogeneous multi-core processors , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[19]  Israel Koren,et al.  Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores , 2011, 2011 International Conference on Parallel Architectures and Compilation Techniques.

[20]  Anuj Pathania,et al.  Price theory based power management for heterogeneous multi-cores , 2014, ASPLOS.

[21]  Vanish Talwar,et al.  Using Asymmetric Single-ISA CMPs to Save Energy on Operating Systems , 2008, IEEE Micro.

[22]  Omer Khan,et al.  Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors , 2011, Trans. High Perform. Embed. Archit. Compil..

[23]  Israel Koren,et al.  Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency , 2012, 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing.

[24]  Umer Liqat,et al.  A Practical Approach for Energy Efficient Scheduling in Multicore Environments by Combining Evolutionary and YDS Algorithms with Faster Energy Estimation , 2015, AIAI.