VLSI architectures for the full-search blockmatching algorithm

Systolic VLSI architectures for an implementation of the full-search block-matching algorithm are described. A large range of data rates can be efficiently covered by the proposed architectures. The input bandwidth problem for the search-area data is solved with on-chip line buffers. Two data input modes are investigated: line-scan mode and block-scan mode. A VLSI realization with a very low transistor count and a small chip area can be achieved by linear arrays in conjunction with compact memory blocks based on three-transistor cells.<<ETX>>

[1]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[2]  P. Pirsch,et al.  Advances in picture coding , 1985, Proceedings of the IEEE.

[3]  Peter Pirsch,et al.  VLSI Architectures For Block Matching Algorithms , 1988, Other Conferences.

[4]  R. Tielert,et al.  A CMOS VLSI chip for filtering of TV pictures in two dimensions , 1986 .

[5]  Ming-Ting Sun,et al.  VLSI Implementation Of Motion Compensation Full-Search Block-Matching Algorithm , 1988, Other Conferences.

[6]  Peter Pirsch,et al.  VLSI architectures for block matching algorithms , 1989, International Conference on Acoustics, Speech, and Signal Processing,.