A Single-Chip Dual-Band 0.25μm CMOS Transceiver for 802.11a/b/g Wireless LAN

This paper presents a dual-band, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, transceiver for IEEE 802.11a/b/g standards in a 0.25mum CMOS process. With a novel architecture and frequency planning, only one voltage-controlled oscillator and frequency synthesizer is required to perform frequency transferring for dual-band operation, and the building blocks of both receiver and transmitter could be shared as many as possible. The fully integrated VCO and frequency synthesizer centered at 3.8GHz achieves an integrated phase noise of 1.35deg rms. The transmitter achieves -33dB EVM at -3dBm output power, and -29dB EVM at -7dBm output power from the integrated preamplifier for 2.4GHz and 5GHz bands respectively. The receiver also exhibits a noise figure of 3dB at 2.4GHz band and 3.8dB at 5GHz band. The transceiver occupies an area of 25mm2

[1]  K.R. Rao,et al.  A single chip CMOS transceiver for 802.11 a/b/g WLANs , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[2]  M. Zargari,et al.  A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[3]  Jan Craninckx,et al.  A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS , 1996 .