Vector Space Theoretic Analysis of Additive Cellular Automata and Its Application for Pseudoexhaustive Test Pattern Generation

A novel scheme for utilizing the regular structure of three neighborhood additive cellular automata (CAs) for pseudoexhaustive test pattern generation is introduced. The vector space generated by a CA can be decomposed into several cyclic subspaces. A cycle corresponding to an m-dimensional cyclic subspace has been shown to pseudoexhaustively test an n-input circuit (n>or=m). Such a cycle is shown to supply a (m-1) bit exhaustive pattern including the all-zeros (m-1)-tuple. Schemes have been reported specifying how one or more subsets of (m-1) cell positions of an n-cell CA can be identified to generate exhaustive patterns in an m-dimensional cyclic subspace. >

[1]  P. P. Chaudhuri,et al.  Built-in self-test structures around cellular automata and counters , 1990 .

[2]  Edward J. McCluskey,et al.  Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudoexhaustive Test Technique , 1986, IEEE Transactions on Computers.

[3]  Solomon W. Golomb,et al.  Shift Register Sequences , 1981 .

[4]  Howard C. Card,et al.  Cellular Automata-Based Signature analysis for Built-in Self-Test , 1990, IEEE Trans. Computers.

[5]  B. Mitra,et al.  A system for synthesis of sequential machines with built-in testability , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[6]  Arnold L. Rosenberg,et al.  Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing , 1983, IEEE Transactions on Computers.

[7]  Howard C. Card,et al.  Cellular automata-based pseudorandom number generators for built-in self-test , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  B. Noble.  Applied Linear Algebra , 1969 .

[9]  Edward J. McCluskey,et al.  Circuits for pseudoexhaustive test pattern generation , 1986, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Donald T. Tang,et al.  Logic Test Pattern Generation Using Linear Codes , 1984, IEEE Transactions on Computers.

[11]  F. R. Gantmakher.  The Theory of Matrices , 1984 .

[12]  Parimal Pal Chaudhuri,et al.  A flexible scheme for state assignment based on characteristics of the FSM , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[13]  C. L. Chen.  Exhaustive Test Pattern Generation Using Cyclic Codes , 1988, IEEE Trans. Computers.

[14]  R. McLeod,et al.  Cellular automata circuits for built-in self test , 1990 .

[15]  Donald T. Tang,et al.  Iterative Exhaustive Pattern Generation for Logic Testing , 1984, IBM J. Res. Dev..

[16]  Donald T. Tang,et al.  Exhaustive Test Pattern Generation with Constant Weight Vectors , 1983, IEEE Transactions on Computers.

[17]  G. E. Sobelman,et al.  An efficient approach to pseudo-exhaustive test generation for BIST design , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[18]  P. Pal Chaudhuri,et al.  Efficient characterisation of cellular automata , 1990 .

[19]  Edward J. McCluskey.  Verification Testing - A Pseudoexhaustive Test Technique , 1984, IEEE Trans. Computers.

[20]  P. P. Chaudhuri,et al.  An efficient on-chip deterministic test pattern generation scheme , 1989, Microprocessing and Microprogramming.

[21]  Parimal Pal Chaudhuri,et al.  Signature analysers based on additive cellular automata , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

[22]  James L. Massey,et al.  Review of 'Error-Correcting Codes, 2nd edn.' (Peterson, W. W., and Weldon, E. J., Jr.; 1972) , 1973, IEEE Trans. Inf. Theory.

[23]  W. W. Peterson,et al.  Error-Correcting Codes. , 1962 .

[24]  ALOKE K. DAS,et al.  On characterization of cellular automata with matrix algebra , 1992, Inf. Sci..