A compact on-chip IR-drop measurement system in 28 nm CMOS technology

A sensor system for measuring the power-ground (PG) noise in very large scale integrated circuits is presented. The proposed system utilizes sensor elements with standard cell dimensions enabling high spatial resolution voltage measurements of power and ground rails. Asynchronous sub-sampling is used to directly convert the analog signals into the digital domain inside the sensors to ensure precise waveform acquisition. Timing signals are derived from a all-digital phase-locked-loop (ADPLL) which guarantees accurate low-noise sampling of the supply waveforms. The sensor system has been implemented in a 28nm CMOS test chip. Simultaneous acquisition of voltage drop and ground bounce at 300 probe points within a 120μm × 120μm macro at 62.5 ps time and up to 250μV voltage resolution shows the capabilities of both, high spatial and high temporal resolution measurement of PG noise.

[1]  Andrew T. Yang,et al.  Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[2]  M. Nagata,et al.  A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits , 2005, IEEE Journal of Solid-State Circuits.

[3]  Kouji Ichikawa,et al.  Measurements and co-simulation of on-chip and on-board AC power noise in digital integrated circuits , 2011, 2011 8th Workshop on Electromagnetic Compatibility of Integrated Circuits.

[4]  M. Nagata,et al.  On-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[5]  D. Hesidenz,et al.  High Speed, High Bandwidth On-Chip Current and Voltage Sensor , 2006, 2006 5th IEEE Conference on Sensors.

[6]  M. Nagata,et al.  Dynamic power-supply and well noise measurement and analysis for high frequency body-biased circuits , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[7]  René Schüffny,et al.  A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.

[9]  Makoto Nagata,et al.  An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Takushi Hashida,et al.  An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration , 2011, IEEE Journal of Solid-State Circuits.

[11]  Y. Yasu,et al.  In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution , 2006, IEEE Journal of Solid-State Circuits.

[12]  M. Nagata,et al.  A built-in technique for probing power-supply noise distribution within large-scale digital integrated circuits , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).