A simulated model for cycle time reduction by acquiring optimal lot size in semiconductor manufacturing

Cycle time reduction is one of the most critical issues in gaining a competitive advantage in wafer fabrication. People widely recognize that lot size reduction can effectively shorten production cycle time. Due to the constraints of conventional equipment and technology, this concept has not been widely applied in wafer fabrication. However, because of the invention of new technology, restrictions on equipment and processes have been reduced in recent years. Wafer lot sizing policy thus becomes an alternative in reducing cycle time. This study develops a simulation model which can acquire optimal lot size to reduce cycle time under different bottleneck loading environments. Simulation experiments based on realistic data from a Taiwan semiconductor fabricator are conducted. Sensitivity analyses of lot sizing impact upon cycle time reduction in wafer fabrication are performed as well. Numerical results demonstrate that the proposed model is sound in acquiring the optimal lot size for cycle time reduction in different loading scenarios. The model can help fabrication managers obtain optimal lot sizes in different bottleneck situations to effectively reduce product cycle time.