A 40nW, Sub-IV Truly ‘Digital’ Reverse Bandgap Reference Using Bulk-Diodes in 16nm FinFET

We present a novel, simple concept to generate a robust voltage reference, which is based on capacitive bias of pn-junctions. The respective PTAT and CTAT signals are sampled from the voltage-decay by means of different timings, and combined through charge sharing. This provides for precise current ratios of N >10000, resulting in exceptionally large PTAT and reverse-bandgap levels. Here, for the first time, the Nwell/Psub diode of a standard CMOS process is utilized in replacement of parasitic BJTs. The measured samples, in 16nm FinFet on 2200μm2 active area, achieve an untrimmed accuracy of ±0.82% (3σ) at 235mV output. Line sensitivity is 0.7mV/100mV, operating at a minimum supply of 0.85V with 47nA power drain. The compact Bandgap circuit is digital to that effect that no amplifiers, resistors, biasing or matching currents are required, neither is it impacted by any analog transistor performance.

[1]  Sanjay Kumar Wadhwa,et al.  High Accuracy, Multi-output Bandgap Reference Circuit in 16nm FinFet , 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

[2]  Yung-Chow Peng,et al.  An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET , 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[3]  Ralf Brederlow,et al.  An Ultra Low Power Bandgap Operational at Supply From 0.75 V , 2012, IEEE Journal of Solid-State Circuits.

[4]  Edward H. Hellen,et al.  Verifying the diode-capacitor circuit voltage decay , 2003 .

[5]  David D. Wentzloff,et al.  5.4 A 32nW bandgap reference voltage operational from 0.5V supply for ultra-low power systems , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.