A 5.2 GHz, 1.7 dB NF low noise amplifier for wireless LAN based on 0.18 um CMOS technology

A high gain, low noise LNA is implemented using inter-stage series resonance technique. This paper reports the implication of the quality factor of the resonating inductor on the LNA performances such as voltage and current gain, noise figure, and power gain. Two versions LNAs with low and high resonating inductors are designed for 5.2 GHz applications based on 0.18 /spl mu/m CMOS technology. Simulation results show power gain of 18.9 dB, NF of 1.7 dB, and OIP3 of 12.9 dBm from the high Q inductor version.

[1]  M. Steyaert,et al.  High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection , 2001 .

[2]  Choong-Yul Cha,et al.  A low power, high gain LNA topology , 2000, ICMMT 2000. 2000 2nd International Conference on Microwave and Millimeter Wave Technology Proceedings (Cat. No.00EX364).

[3]  E. H. Westerwick.  A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[4]  A.A. Abidi,et al.  A 2.4-GHz low-IF receiver for wideband WLAN in 6-/spl mu/m CMOS-architecture and front-end , 2000, IEEE Journal of Solid-State Circuits.

[5]  Thomas H. Lee.  The Design of CMOS Radio-Frequency Integrated Circuits , 1998 .

[6]  M.N. El-Gamal,et al.  2.4-5.8 GHz CMOS LNA's using integrated inductors , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[7]  J. Colvin,et al.  Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology , 1999 .

[8]  T.H. Lee,et al.  A 1.5 V, 1.5 GHz CMOS low noise amplifier , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[9]  H.R. Rategh,et al.  A 5-GHz CMOS wireless LAN receiver front end , 2000, IEEE Journal of Solid-State Circuits.

[10]  Sang-Gug Lee,et al.  A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance , 2003, IEEE J. Solid State Circuits.

[11]  Sang-Gug Lee,et al.  A 5.2GHz LNA in 0.35µm CMOS utilizing inter–stage series resonance and optimizing the substrate resistance , 2002 .

[12]  Wong-Sun Kim,et al.  A 2.4 GHz CMOS low noise amplifier using an inter-stage matching inductor , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).