Achieving SLC performance with MLC flash memory

Although the Multi-Level-Cell technique is widely adopted by flash-memory vendors to boost the chip density and to lower the cost, it results in serious performance and reliability problems. Different from the past work, a new cell programming method is proposed to not only significantly improve the chip performance but also reduce the potential bit error rate. In particular, a Single-Level-Cell-like programming style is proposed to better explore the threshold-voltage relationship to denote different Multi-Level-Cell bit information, which in turn drastically provides a larger window of threshold voltage similar to that found in Single-Level-Cell chips. It could result in less programming iterations and simultaneously a much less reliability problem in programming flash-memory cells. In the experiments, the new programming style could accelerate the programming speed up to 742% and even reduce the bit error rate up to 471% for Multi-Level-Cell pages.

[1]  Dongkun Shin,et al.  KAST: K-associative sector translation for NAND flash memory in real-time systems , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Sang Lyul Min,et al.  A space-efficient flash translation layer for CompactFlash systems , 2002, IEEE Trans. Consumer Electron..

[3]  Shih-Hung Chen,et al.  A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL) , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[4]  Eui-Young Chung,et al.  Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices , 2009, IEEE Transactions on Consumer Electronics.

[5]  Dongkun Shin,et al.  Flash-Aware RAID Techniques for Dependable and High-Performance Flash Memory SSD , 2011, IEEE Transactions on Computers.

[6]  Young-Hyun Jun,et al.  A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[7]  K. Hsieh,et al.  Future challenges of flash memory technologies , 2009 .

[8]  Yeong-Taek Lee,et al.  A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.

[9]  Zili Shao,et al.  MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[10]  Paul H. Siegel,et al.  Characterizing flash memory: Anomalies, observations, and applications , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[11]  Yoon-Hee Choi,et al.  Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming , 2014, IEEE Journal of Solid-State Circuits.

[12]  Won-Tae Kim,et al.  19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[13]  Y. Iwata,et al.  Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[14]  Tei-Wei Kuo,et al.  An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[15]  A. Visconti,et al.  Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories , 2009, IEEE Transactions on Electron Devices.

[16]  Bharadwaj Veeravalli,et al.  WAFTL: A workload adaptive flash translation layer with data partition , 2011, 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST).

[17]  Il Han Park,et al.  Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH , 2013, IEEE J. Solid State Circuits.

[18]  Luis A. Lastras,et al.  Write amplification reduction in NAND Flash through multi-write coding , 2010, 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST).

[19]  Youngjae Kim,et al.  DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.

[20]  Young-Ho Lim,et al.  A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme , 1995 .

[21]  Ki-Whan Song,et al.  Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH , 2013, IEEE Journal of Solid-State Circuits.

[22]  Sang-Won Lee,et al.  FAST: An Efficient Flash Translation Layer for Flash Memory , 2006, EUC Workshops.

[23]  YunSeung Shin,et al.  Non-volatile memory technologies for beyond 2010 , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[24]  Tei-Wei Kuo,et al.  A reliability enhancement design under the flash translation layer for MLC-based flash-memory storage systems , 2013, TECS.