Microarchitecture level power and thermal simulation considering temperature dependent leakage model
暂无分享,去创建一个
Lei He | Weiping Liao | Fei Li
[1] R.W. Brodersen,et al. A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.
[2] Himanshu Kaul,et al. Future performance challenges in nanometer design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[3] G. Sohi,et al. A static power model for architects , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.
[4] Lei He,et al. Leakage power modeling and reduction with data retention , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..
[5] W. Robert Daasch,et al. TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator , 2000, PACS.
[6] Vikas Agarwal,et al. Static energy reduction techniques for microprocessor caches , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.
[7] Mahmut T. Kandemir,et al. The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.