IC Design of 2Ms/s 10-bit SAR ADC with Low Power

This paper presents the development of a 2 Ms/s 10-bit very low-power CMOS SAR ADC which is realized in a 0.35 mum CMOS process. The design combines a capacitor array DAC, a dual-cross coupled pair comparator, and SAR digital logic to create 8 effective bits while consuming less than 3 mW with a 3.3 V power supply.