Design of modular digital circuits for testability
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[1] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[2] Andrew Kusiak,et al. Intelligent Manufacturing Systems , 1990 .
[3] R. Langlois,et al. Networks and innovation in a modular system: Lessons from the microcomputer and stereo component industries , 1992 .
[4] Andrew Kusiak,et al. Reengineering of design and manufacturing processes , 1994 .
[5] J. Paul Roth,et al. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits , 1967, IEEE Trans. Electron. Comput..
[6] Andrew Kusiak,et al. Performance analysis of modular products , 1996 .
[7] Ron Sanchez,et al. Strategic product creation: Managing new interactions of technology, markets, and organizations , 1996 .
[8] Füsun Özgüner,et al. 9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits , 1978, IEEE Transactions on Computers.
[9] Erwin Trischler,et al. Ten: A concurrent test engineering environment , 1994, IEEE Design & Test of Computers.
[10] L. H. Goldstein,et al. Controllability/observability analysis of digital circuits , 1978 .
[11] John P. Hayes. On Modifying Logic Networks to Improve Their Diagnosability , 1974, IEEE Transactions on Computers.
[12] David W. Rosen,et al. Implications of Modularity on Product Design for the Life Cycle , 1998 .
[13] L. H. Goldstein,et al. SCOAP: Sandia Controllability/Observability Analysis Program , 1988, 17th Design Automation Conference.
[14] Jon L. Turino. Design to test , 1990 .
[15] Andrew Kusiak,et al. Development of modular products , 1996 .
[16] Elizabeth M. Rudnick,et al. Non-Scan Design-for-Testability Techniques for Sequential Circuits , 1993, 30th ACM/IEEE Design Automation Conference.
[17] Durward K. Sobek,et al. The Second Toyota Paradox: How Delaying Decisions Can Make Better Cars Faster , 1995 .
[18] G. Gilder. Microcosm: The Quantum Revolution In Economics And Technology , 1989 .
[19] Shoab Ahmed Khan,et al. System Partitioning of MCMs for Low Power , 1995, IEEE Des. Test Comput..
[20] Hideo Fujiwara,et al. On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.
[21] Dong Sam Ha,et al. On using signature registers as pseudorandom pattern generators in built-in self-testing , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[22] Janak H. Patel,et al. An optimization based approach to the partial scan design problem , 1990, Proceedings. International Test Conference 1990.
[23] M. Abramovici,et al. SMART And FAST: Test Generation for VLSI Scan-Design Circuits , 1986, IEEE Design & Test of Computers.
[24] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[25] D. V. Steward. Partitioning and Tearing Systems of Equations , 1965 .
[26] Giovanni De Micheli,et al. Algorithms for technology mapping based on binary decision diagrams and on Boolean operations , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[27] Karl T. Ulrich,et al. Fundamentals of Product Modularity , 1994 .
[28] Robert J. Linhardt,et al. System Utilization of Large-Scale Integration , 1967, IEEE Trans. Electron. Comput..
[29] P. Goel. AN IMPLICIT ENUMERATION ALGORITHM TO GENERATE TESTS FOR COMBINATIONAL LOGIC CIRCUITS , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..
[30] Andrew Kusiak,et al. Concurrent engineering: decomposition and scheduling of design activities , 1990 .
[31] Arthur D. Friedman,et al. Test Point Placement to Simplify Fault Detection , 1974, IEEE Transactions on Computers.
[32] Paul T. Kidd,et al. Agile Manufacturing: Forging New Frontiers , 1994 .
[33] Robert C. Aitken. An Overview of Test Synthesis Tools , 1995, IEEE Des. Test Comput..
[34] Kenneth P. Parker,et al. The Boundary-Scan Handbook , 1992, Springer US.