An Efficient Finite Element Method for Submicron IC Capacitance Extraction

We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the conductor charges are approximated by a piece-wise linear function on a web of edges located on the surface of the conductors. This yields a system of Green's function integral equations that is solved by a novel approximate matrix inversion technique that only utilizes the entries corresponding to pairs of finite elements that are physically close to each other. With N representing the size of the layout, this results in time and space complexities of O(N) and O(PIN) respectively. The method has been implemented in an efficient layout to circuit extractor and experimental results are presented.

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