The network architecture of the Connection Machine CM-5 (extended abstract)

The Connection Machine Model CM-5 Supercomputer is a massively parallel computer system designed to offer performance in the range of 1 teraflops (1012 floating-point operations per second). The CM-5 obtains its high performance while offering ease of programming, flexibility, and reliability. The machine contains three communication networks: a data network, a control network, and a diagnostic network. This paper describes the organization of these three networks and how they contribute to the design goals of the CM-5.

[1]  Bruce M. Maggs,et al.  Universal packet routing algorithms , 1988, [Proceedings 1988] 29th Annual Symposium on Foundations of Computer Science.

[2]  Charles L. Seitz,et al.  The cosmic cube , 1985, CACM.

[3]  Rajiv Gupta.  The fuzzy barrier: a mechanism for high speed synchronization of processors , 1989, ASPLOS III.

[4]  Harry F. Jordan,et al.  A multi-microprocessor system for finite element structural analysis , 1979 .

[5]  Michel Dubois,et al.  Scalable shared-memory multiprocessor architectures , 1990, Computer.

[6]  Leonard Kleinrock,et al.  Virtual Cut-Through: A New Computer Communication Switching Technique , 1979, Comput. Networks.

[7]  Robert C. Zak,et al.  An IEEE 1149.1 compliant testability architecture with internal scan , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[8]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[9]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[10]  Guy E. Blelloch,et al.  Vector Models for Data-Parallel Computing , 1990 .

[11]  L. Kleinrock,et al.  Principles and lessons in packet communications , 1978, Proceedings of the IEEE.

[12]  Daniel R. Cassiday,et al.  Functional VLSI design verification methodology for the CM-5 massively parallel supercomputer , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[13]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[14]  W. Daniel Hillis,et al.  Data parallel algorithms , 1986, CACM.

[15]  Frederica Darema,et al.  A single-program-multiple-data computational model for EPEX/FORTRAN , 1988, Parallel Comput..

[16]  Charles E. Leiserson,et al.  Randomized Routing on Fat-Trees , 1989, Adv. Comput. Res..

[17]  Michael J. Flynn,et al.  Very high-speed computing systems , 1966 .

[18]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .