Data path synthesis for BIST with low area overhead

This paper presents an attempt towards design quality improvement by incorporating of self-testability features during data path (high-level) synthesis. This method is based on the use of test resource sharing possibilities to improve the self-testability of the circuit. This is achieved by incorporating testability constraints during register assignment. Experimental results are presented to demonstrate the effectiveness of the proposed data path synthesis for BIST approach.

[1]  Alice C. Parker,et al.  Predicting system-level area and delay for pipelined and nonpipelined designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Melvin A. Breuer,et al.  Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead , 1995, 32nd Design Automation Conference.

[3]  Manfred Padberg,et al.  Location, Scheduling, Design and Integer Programming , 2011, J. Oper. Res. Soc..

[4]  LaNae J. Avra,et al.  ALLOCATION AND ASSIGNMENT IN HIGH-LEVEL SYNTHESIS FOR SELF-TESTABLE DATA PATHS , 1991, 1991, Proceedings. International Test Conference.

[5]  Mike Tien-Chien Lee,et al.  High-Level Test Synthesis of Digital VLSI Circuits , 1997 .

[6]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Haidar Harmanani,et al.  SYNTEST: a method for high-level SYNthesis with self-TESTability , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.