Study of pattern area reduction with FinFET and SGT for LSI

The pattern area reduction with SGT and FinFET for LSI, such as inverter, NAND gates, full adder, and row decoder has been newly described. With small channel width of 8F the pattern area of inverter, NAND gates and full adders with SGT can be reduced compared with that with FinFET. This results are useful for designing system LSI for communications. With larger channel width than 8F the pattern area of inverter, NAND gates and full adders with SGT has the tendency to become larger than that with FinFET. This results are useful for designing system LSI for cell library and high end MPU. Furthermore, for designing core circuit, such as row decoder and sense amplifier, smaller pattern area can be realized with SGT compared with that with FinFET.

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