36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control

Mathematically secure cryptographic algorithms leak side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical side-channel analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include current equalizer [1], series LDO [2], IVR [3], enhancing protection up to 10M traces. Recently, current domain signature attenuation [4] and randomized NL-LDO cascaded with arithmetic countermeasures [5] achieved $\gt1\mathrm{B}$ minimum traces to disclosure (MTD) with a single and two countermeasures, respectively. Among these, the highest protection with a single strategy is achieved using signature attenuation [4], [6], which utilized a current source making the supply current mostly constant. While being highly resilient to SCA, [4] required analog-biased cascode current sources and an analog bleed path, making it not easily scalable across different technology generations. Conversely, [2], [5] are synthesizable but a single countermeasure only achieved moderate protection (up to 10M MTD). This work embraces the concept of signature attenuation in the current domain, but makes it fully-synthesizable with digital current sources, control loop and the bleed to increase the MTD from 10M [5] to $250\mathrm{M} (25 \times $ improvement, Fig. 36.2.1) using a single synthesizable countermeasure. Finally, combining the digital signature attenuation circuit (DSAC) with a second synthesizable generic technique in the form of a time-varying transfer function (TVTF), this work achieves an MTD $\gt1.25\mathrm{B}$ for both EM and power SCA.

[1]  Sanu Mathew,et al.  8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[2]  David Blaauw,et al.  Secure AES engine with a local switched-capacitor current equalizer , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[3]  Sanu Mathew,et al.  27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[4]  Santosh Ghosh,et al.  Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS , 2020, 2020 IEEE Custom Integrated Circuits Conference (CICC).

[5]  Sanu Mathew,et al.  A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures , 2020, 2020 IEEE Symposium on VLSI Circuits.