A microcode-based memory BIST implementing modified march algorithm

A new microcode-based BIST (built-in self test) circuitry for embedded memory components is proposed in this paper. The memory BIST implements march algorithms which are slightly modified by adopting DOF (degree of freedom) concept to detect ADOFs (address decoder open faults) on top of conventional stuck faults. Furthermore it is shown that the march BIST modified can capture a few NPSFs (neighborhood pattern sensitive faults) coupled with the cellular automata address generator and patterns. The microcode-based memory BIST proposed lends itself to performing different combinations of march and retention tests with less microcode storage than the other approaches.

[1]  Shujian Zhang,et al.  2-by-n Hybrid Cellular Automata with Regular Configuration: Theory and Application , 1999, IEEE Trans. Computers.

[2]  Ki Tae Park,et al.  Automatic failure analysis system for high density DRAM , 1994, Proceedings., International Test Conference.

[3]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[4]  Paul H. Bardell.  Analysis of cellular automata used as pseudorandom pattern generators , 1990, Proceedings. International Test Conference 1990.

[5]  Hiroki Koike,et al.  A BIST scheme using microprogram ROM for large capacity memories , 1990, Proceedings. International Test Conference 1990.

[6]  Kewal K. Saluja,et al.  A built-in self-test algorithm for row/column pattern sensitive faults in RAMs , 1990 .

[7]  Ad J. van de Goor,et al.  Semiconductor manufacturing process monitoring using built-in self-test for embedded memories , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[8]  T. W. Williams,et al.  Detection of CMOS address decoder open faults with March and pseudo random memory tests , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Shambhu J. Upadhyaya,et al.  On programmable memory built-in self test architectures , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[10]  Paul H. Bardell,et al.  Self-Test of Random Access Memories , 1985, ITC.

[11]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[12]  Pinaki Mazumder,et al.  Testing and Testable Design of High-Density Random-Access Memories , 1996 .

[13]  Manoj Sachdev.  Open Defects in CMOS RAM Address Decoders , 1997, IEEE Des. Test Comput..

[14]  J. Otterstedt,et al.  Integration of non-classical faults in standard March tests , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).