论文信息 - An efficient architecture for the AES mix columns operation

An efficient architecture for the AES mix columns operation

In this paper, a compact architecture for the AES mix columns operation and its inverse is presented. The hardware implementation is compared with previous work done in this area. We show that our design has a lower gate count than other designs that implement both the forward and the inverse mix columns operation.

Hua Li | Zac Friggstad | Hua Li | Z. Friggstad

[1] Patrick Schaumont,et al. A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[2] Sandra Dominikus,et al. A Highly Regular and Scalable AES Hardware Architecture , 2003, IEEE Trans. Computers.

[3] Vijay Kumar,et al. Efficient Rijndael Encryption Implementation with Composite Field Arithmetic , 2001, CHES.